From 1b15dca5065a1a12c097afbb6eac6a8ff8d8e20a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 12 Oct 2020 15:26:51 -0700
Subject: When prefixing with a data, eagly get local name (#1614)

Fixes #1606

Previously, the Data itself would be put on the prefix stack and its
full name would be used as the prefix for subsequent names. This meant
that prefixes would grow quadratically as the prefix is present both on
the Data pushed to the stack, and on the stack itself. This is fixed by
just using the "local" name of the Data being pushed on the stack.

A related issue is deferring the name resolution. This led to unintuitive
behavior when the name of a Data used as a prefix is overridden later
(usually when the Data is a return value). The overriding name would
show up in prefixes twice instead of once. It is much more intuitive to
grab the name at the moment of the connection creating the prefix rather
than deferring to later.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/chiselTests/naming/PrefixSpec.scala | 57 +++++++++++++++++++++-
 1 file changed, 55 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala
index 888ce1ba..27a9fd39 100644
--- a/src/test/scala/chiselTests/naming/PrefixSpec.scala
+++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala
@@ -69,8 +69,6 @@ class PrefixSpec extends ChiselPropSpec with Utils {
 
   property("Prefixing seeded with signal") {
     class Test extends MultiIOModule {
-      @treedump
-      @dump
       def builder(): UInt = {
         val wire = Wire(UInt(3.W))
         wire := 3.U
@@ -345,4 +343,59 @@ class PrefixSpec extends ChiselPropSpec with Utils {
         ))
     }
   }
+
+  property("Connections should use the non-prefixed name of the connected Data") {
+    class Test extends MultiIOModule {
+      prefix("foo") {
+        val x = Wire(UInt(8.W))
+        x := {
+          val w = Wire(UInt(8.W))
+          w := 3.U
+          w + 1.U
+        }
+      }
+    }
+    aspectTest(() => new Test) {
+      top: Test =>
+        Select.wires(top).map(_.instanceName) should be (List("foo_x", "foo_x_w"))
+    }
+  }
+
+  property("Connections to aggregate fields should use the non-prefixed aggregate name") {
+    class Test extends MultiIOModule {
+      prefix("foo") {
+        val x = Wire(new Bundle { val bar = UInt(8.W) })
+        x.bar := {
+          val w = Wire(new Bundle { val fizz = UInt(8.W) })
+          w.fizz := 3.U
+          w.fizz + 1.U
+        }
+      }
+    }
+    aspectTest(() => new Test) {
+      top: Test =>
+        Select.wires(top).map(_.instanceName) should be (List("foo_x", "foo_x_bar_w"))
+    }
+  }
+
+
+  property("Prefixing with wires in recursive functions should grow linearly") {
+    class Test extends MultiIOModule {
+      def func(bools: Seq[Bool]): Bool = {
+        if (bools.isEmpty) true.B
+        else {
+          val w = Wire(Bool())
+          w := bools.head && func(bools.tail)
+          w
+        }
+      }
+      val in = IO(Input(Vec(4, Bool())))
+      val x = func(in)
+    }
+    aspectTest(() => new Test) {
+      top: Test =>
+        Select.wires(top).map(_.instanceName) should be (List("x", "x_w_w", "x_w_w_w", "x_w_w_w_w"))
+    }
+
+  }
 }
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