From 0ca4ce23400d3624f8f617aa8ae21880d8430c2e Mon Sep 17 00:00:00 2001
From: Boyang Han
Date: Mon, 6 Sep 2021 21:27:51 -0700
Subject: Test case rework

---
 src/test/scala/chiselTests/util/experimental/PlaSpec.scala | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
index ced4f9dd..8af5c936 100644
--- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
@@ -52,14 +52,13 @@ class PlaSpec extends ChiselFlatSpec {
   "#2112" should "be generated correctly" in {
     assertTesterPasses(new BasicTester {
       val table = Seq(
-        (BitPat("b0"), BitPat("b?0")),
-        (BitPat("b1"), BitPat("b?1")),
-        (BitPat("b?"), BitPat("b1?")),
+        (BitPat("b000"), BitPat("b?01")),
+        (BitPat("b111"), BitPat("b?01")),
       )
       table.foreach { case (i, o) =>
         val (plaIn, plaOut) = pla(table)
         plaIn := WireDefault(i.value.U(3.W))
-        chisel3.assert(plaOut === o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+        chisel3.assert(o === plaOut, "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
       }
       stop()
     })
-- 
cgit v1.2.3