From 06c5e3e82f7dd4aa8ce159aa4c13b9bc36abce96 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 1 Feb 2019 03:17:15 -0500 Subject: Add ChiselOptionsView Co-Authored-By: Schuyler Eldridge Co-Authored-By: chick Signed-off-by: Schuyler Eldridge --- .../chiselTests/stage/ChiselOptionsViewSpec.scala | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 src/test/scala/chiselTests/stage/ChiselOptionsViewSpec.scala (limited to 'src/test') diff --git a/src/test/scala/chiselTests/stage/ChiselOptionsViewSpec.scala b/src/test/scala/chiselTests/stage/ChiselOptionsViewSpec.scala new file mode 100644 index 00000000..7dbeb9fa --- /dev/null +++ b/src/test/scala/chiselTests/stage/ChiselOptionsViewSpec.scala @@ -0,0 +1,40 @@ +// See LICENSE for license details. + +package chiselTests.stage + +import org.scalatest.{FlatSpec, Matchers} + +import firrtl.options.Viewer.view + +import chisel3.stage._ +import chisel3.internal.firrtl.Circuit + +class ChiselOptionsViewSpec extends FlatSpec with Matchers { + + behavior of ChiselOptionsView.getClass.getName + + it should "construct a view from an AnnotationSeq" in { + val bar = Circuit("bar", Seq.empty, Seq.empty) + val annotations = Seq( + NoRunFirrtlCompilerAnnotation, + PrintFullStackTraceAnnotation, + ChiselOutputFileAnnotation("foo"), + ChiselCircuitAnnotation(bar) + ) + val out = view[ChiselOptions](annotations) + + info("runFirrtlCompiler was set to false") + out.runFirrtlCompiler should be (false) + + info("printFullStackTrace was set to true") + out.printFullStackTrace should be (true) + + info("outputFile was set to 'foo'") + out.outputFile should be (Some("foo")) + + info("chiselCircuit was set to circuit 'bar'") + out.chiselCircuit should be (Some(bar)) + + } + +} -- cgit v1.2.3