From 815b1c3cb311b7f4dfb7a2f00e0e2d62795bdc6b Mon Sep 17 00:00:00 2001
From: Jack
Date: Fri, 11 Nov 2016 14:37:03 -0800
Subject: Add checks for misuse or omission of Module()

Implemented by adding a Boolean to check for alternating invocations of object
Module.apply and the constructor of abstract class Module.
Fixes #192
---
 src/test/scala/chiselTests/AnnotatingExample.scala |  4 +-
 src/test/scala/chiselTests/ChiselSpec.scala        |  2 +-
 src/test/scala/chiselTests/DeqIOSpec.scala         | 62 ----------------------
 src/test/scala/chiselTests/Module.scala            | 34 ++++++++++++
 4 files changed, 37 insertions(+), 65 deletions(-)
 delete mode 100644 src/test/scala/chiselTests/DeqIOSpec.scala

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala
index c84edf86..04228d6b 100644
--- a/src/test/scala/chiselTests/AnnotatingExample.scala
+++ b/src/test/scala/chiselTests/AnnotatingExample.scala
@@ -141,5 +141,5 @@ object MyDriver extends BackendCompilationUtilities {
   /**
     * illustrates a chisel3 style driver that, annotations can only processed within this structure
     */
-  def buildAnnotatedCircuit[T <: Module](gen: () => T): Map[String, String] = MyBuilder.build(Module(gen()))
-}
\ No newline at end of file
+  def buildAnnotatedCircuit[T <: Module](gen: () => T): Map[String, String] = MyBuilder.build(gen())
+}
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index d335bdf6..7b915c09 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -28,7 +28,7 @@ trait ChiselRunners extends Assertions {
 class ChiselFlatSpec extends FlatSpec with ChiselRunners with Matchers
 
 /** Spec base class for property-based testers. */
-class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks {
+class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks with Matchers {
 
   // Constrain the default number of instances generated for every use of forAll.
   implicit override val generatorDrivenConfig =
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
deleted file mode 100644
index d41c50e5..00000000
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ /dev/null
@@ -1,62 +0,0 @@
-// See LICENSE for license details.
-
-package chiselTests
-
-import chisel3._
-import chisel3.testers.BasicTester
-import chisel3.util._
-
-/**
-  * Created by chick on 2/8/16.
-  */
-class UsesDeqIOInfo extends Bundle {
-  val test_width = 32
-
-  val info_data = UInt.width(test_width)
-}
-
-class UsesDeqIO extends Module {
-  val io = IO(new Bundle {
-    val in = chisel3.util.DeqIO(new UsesDeqIOInfo)
-    val out = chisel3.util.EnqIO(new UsesDeqIOInfo)
-  })
-}
-
-class DeqIOSpec extends ChiselFlatSpec {
-  runTester {
-    new BasicTester {
-      val dut = new UsesDeqIO
-/*
-      "DeqIO" should "set the direction of it's parameter to INPUT" in {
-        assert(dut.io.in.bits.info_data.dir === INPUT)
-      }
-      "DeqIO" should "create a valid input and ready output" in {
-        assert(dut.io.in.valid.dir === INPUT)
-        assert(dut.io.in.ready.dir === OUTPUT)
-      }
-      "EnqIO" should "set the  direction of it's parameter OUTPUT" in {
-        assert(dut.io.out.bits.info_data.dir === OUTPUT)
-      }
-      "EnqIO" should "create a valid input and ready output" in {
-        assert(dut.io.out.valid.dir === OUTPUT)
-        assert(dut.io.out.ready.dir === INPUT)
-      }
-
-      val in_clone = dut.io.in.cloneType
-      val out_clone = dut.io.out.cloneType
-
-      "A deqIO device" should "clone itself with it's directions intact" in {
-        assert(dut.io.in.bits.info_data.dir == in_clone.bits.info_data.dir)
-        assert(dut.io.in.ready.dir == in_clone.ready.dir)
-        assert(dut.io.in.valid.dir == in_clone.valid.dir)
-      }
-
-      "A enqIO device" should "clone itself with it's directions intact" in {
-        assert(dut.io.out.bits.info_data.dir == out_clone.bits.info_data.dir)
-        assert(dut.io.out.ready.dir == out_clone.ready.dir)
-        assert(dut.io.out.valid.dir == out_clone.valid.dir)
-      }
-      */
-    }
-  }
-}
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 7a4050db..c902d073 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -69,6 +69,22 @@ class ModuleWhen extends Module {
   } otherwise { io.s.out := io.s.in }
 }
 
+class ModuleForgetWrapper extends Module {
+  val io = IO(new SimpleIO)
+  val inst = new PlusOne
+}
+
+class ModuleDoubleWrap extends Module {
+  val io = IO(new SimpleIO)
+  val inst = Module(Module(new PlusOne))
+}
+
+class ModuleRewrap extends Module {
+  val io = IO(new SimpleIO)
+  val inst = Module(new PlusOne)
+  val inst2 = Module(inst)
+}
+
 class ModuleSpec extends ChiselPropSpec {
 
   property("ModuleVec should elaborate") {
@@ -88,4 +104,22 @@ class ModuleSpec extends ChiselPropSpec {
   }
 
   ignore("ModuleWhenTester should return the correct result") { }
+
+  property("Forgetting a Module() wrapper should result in an error") {
+    (the [ChiselException] thrownBy {
+      elaborate { new ModuleForgetWrapper }
+    }).getMessage should include("attempted to instantiate a Module without wrapping it")
+  }
+
+  property("Double wrapping a Module should result in an error") {
+    (the [ChiselException] thrownBy {
+      elaborate { new ModuleDoubleWrap }
+    }).getMessage should include("Called Module() twice without instantiating a Module")
+  }
+
+  property("Rewrapping an already instantiated Module should result in an error") {
+    (the [ChiselException] thrownBy {
+      elaborate { new ModuleRewrap }
+    }).getMessage should include("This is probably due to rewrapping a Module instance")
+  }
 }
-- 
cgit v1.2.3


From 822160cc8e76e70643fb56707bb39f6f7526b6fd Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 22 Sep 2016 22:38:33 -0700
Subject: Add support for parameterized BlackBoxes

Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.

Resolves #289
---
 src/test/scala/chiselTests/BlackBox.scala | 49 ++++++++++++++++++++++++++-----
 1 file changed, 41 insertions(+), 8 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 344754e1..d8821134 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -6,6 +6,7 @@ import java.io.File
 import org.scalatest._
 
 import chisel3._
+import chisel3.experimental._
 import chisel3.testers.BasicTester
 import chisel3.util._
 //import chisel3.core.ExplicitCompileOptions.Strict
@@ -84,27 +85,55 @@ class BlackBoxWithClockTester extends BasicTester {
   when(end) { stop() }
 }
 
-/*
-// Must determine how to handle parameterized Verilog
-class BlackBoxConstant(value: Int) extends BlackBox {
-  val io = IO(new Bundle() {
-    val out = Output(UInt(width=log2Up(value)))
+class BlackBoxConstant(value: Int) extends BlackBox(
+    Map("VALUE" -> value, "WIDTH" -> log2Up(value + 1))) {
+  require(value >= 0, "value must be a UInt!")
+  val io = IO(new Bundle {
+    val out = UInt(width = log2Up(value + 1)).asOutput
+  })
+}
+
+class BlackBoxStringParam(str: String) extends BlackBox(Map("STRING" -> str)) {
+  val io = IO(new Bundle {
+    val out = UInt(width = 32)
+  })
+}
+
+class BlackBoxRealParam(dbl: Double) extends BlackBox(Map("REAL" -> dbl)) {
+  val io = IO(new Bundle {
+    val out = UInt(width = 64)
+  })
+}
+
+class BlackBoxTypeParam(w: Int, raw: String) extends BlackBox(Map("T" -> RawParam(raw))) {
+  val io = IO(new Bundle {
+    val out = UInt(width = w)
   })
-  override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
 }
 
 class BlackBoxWithParamsTester extends BasicTester {
   val blackBoxOne  = Module(new BlackBoxConstant(1))
-  val blackBoxFour = Module(new BlackBoxConstant(4))
+  val blackBoxFour  = Module(new BlackBoxConstant(4))
+  val blackBoxStringParamOne = Module(new BlackBoxStringParam("one"))
+  val blackBoxStringParamTwo = Module(new BlackBoxStringParam("two"))
+  val blackBoxRealParamOne = Module(new BlackBoxRealParam(1.0))
+  val blackBoxRealParamNeg = Module(new BlackBoxRealParam(-1.0))
+  val blackBoxTypeParamBit = Module(new BlackBoxTypeParam(1, "bit"))
+  val blackBoxTypeParamWord = Module(new BlackBoxTypeParam(32, "bit [31:0]"))
 
   val (cycles, end) = Counter(Bool(true), 4)
 
   assert(blackBoxOne.io.out  === UInt(1))
   assert(blackBoxFour.io.out === UInt(4))
+  assert(blackBoxStringParamOne.io.out === UInt(1))
+  assert(blackBoxStringParamTwo.io.out === UInt(2))
+  assert(blackBoxRealParamOne.io.out === UInt(0x3ff0000000000000L))
+  assert(blackBoxRealParamNeg.io.out === UInt(BigInt("bff0000000000000", 16)))
+  assert(blackBoxTypeParamBit.io.out === UInt(1))
+  assert(blackBoxTypeParamWord.io.out === UInt("hdeadbeef", 32))
 
   when(end) { stop() }
 }
-*/
 
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
@@ -119,4 +148,8 @@ class BlackBoxSpec extends ChiselFlatSpec {
     assertTesterPasses({ new BlackBoxWithClockTester },
         Seq("/BlackBoxTest.v"))
   }
+  "BlackBoxes with parameters" should "work" in {
+    assertTesterPasses({ new BlackBoxWithParamsTester },
+        Seq("/BlackBoxTest.v"))
+  }
 }
-- 
cgit v1.2.3


From 667a26bddb6133e8b243061f8a5fc5fe586cc1ae Mon Sep 17 00:00:00 2001
From: ducky
Date: Tue, 25 Oct 2016 13:46:44 -0700
Subject: Range macro initial impl

---
 src/test/scala/chiselTests/RangeMacroTest.scala | 31 +++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 src/test/scala/chiselTests/RangeMacroTest.scala

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
new file mode 100644
index 00000000..797c75c4
--- /dev/null
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -0,0 +1,31 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import scala.language.experimental.macros
+import org.scalatest._
+import org.scalatest.prop._
+import chisel3.testers.BasicTester
+
+package object rangeMacroTest {
+
+implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+  def range(args: Any*): Unit = macro chisel3.internal.RangeTransform.apply
+}
+
+}
+
+import rangeMacroTest._
+
+/** Comprehensive test of static range parsing functionality.
+  * Note: negative (failure) conditions can't be tested because they will fail at compile time,
+  * before the testing environment is entered.
+  */
+@dump
+class RangeMacroTest extends ChiselPropSpec {
+  property("Range macros should work") {
+    def ducks() = {2}
+    range"  (0, ${ducks}]   "
+  }
+}
-- 
cgit v1.2.3


From 4245c8c31749d9031da4915708bb23ec82a56da2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Tue, 25 Oct 2016 16:59:20 -0700
Subject: Better testing, better parsing

---
 src/test/scala/chiselTests/RangeMacroTest.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
index 797c75c4..d6c51704 100644
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -25,7 +25,7 @@ import rangeMacroTest._
 @dump
 class RangeMacroTest extends ChiselPropSpec {
   property("Range macros should work") {
-    def ducks() = {2}
-    range"  (0, ${ducks}]   "
+    range"(0,${1+1}]"
+    range"  (  0  ,  ${1+1}  ]  "
   }
 }
-- 
cgit v1.2.3


From dd28ef5d95e49c2822f9e37e8011ceab69cad532 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 26 Oct 2016 14:48:00 -0700
Subject: Rename RangeMacro, remove nameprop deps

---
 src/test/scala/chiselTests/RangeMacroTest.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
index d6c51704..88a0730f 100644
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -22,8 +22,7 @@ import rangeMacroTest._
   * Note: negative (failure) conditions can't be tested because they will fail at compile time,
   * before the testing environment is entered.
   */
-@dump
-class RangeMacroTest extends ChiselPropSpec {
+class RangeMacroSpec extends ChiselPropSpec {
   property("Range macros should work") {
     range"(0,${1+1}]"
     range"  (  0  ,  ${1+1}  ]  "
-- 
cgit v1.2.3


From 22406a589c4a3f8de42a9f5c988201f474c11282 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 9 Nov 2016 16:23:52 -0800
Subject: simple test that range interpolator works with UInt factory method

---
 src/test/scala/chiselTests/RangeMacroTest.scala |  9 ---------
 src/test/scala/chiselTests/RangeSpec.scala      | 17 +++++++++++++++++
 2 files changed, 17 insertions(+), 9 deletions(-)
 create mode 100644 src/test/scala/chiselTests/RangeSpec.scala

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
index 88a0730f..cafff1d2 100644
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -8,15 +8,6 @@ import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
 
-package object rangeMacroTest {
-
-implicit class ChiselRange(val sc: StringContext) extends AnyVal {
-  def range(args: Any*): Unit = macro chisel3.internal.RangeTransform.apply
-}
-
-}
-
-import rangeMacroTest._
 
 /** Comprehensive test of static range parsing functionality.
   * Note: negative (failure) conditions can't be tested because they will fail at compile time,
diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
new file mode 100644
index 00000000..edaff8aa
--- /dev/null
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import org.scalatest.{Matchers, FreeSpec}
+
+class RangeSpec extends FreeSpec with Matchers {
+  "Ranges can be specified for UInt, SInt, and FixedPoint" - {
+    "to specify a UInt" in {
+      val x = UInt(range"[0, 7)")
+      x.getWidth should be (3)
+
+      println(range"[4,32)")
+    }
+ }
+}
-- 
cgit v1.2.3


From b39b08b6d489ab6d2dc9bb8a40a87c4ac5834828 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Wed, 9 Nov 2016 16:25:34 -0800
Subject: Delete RangeMacroTest now that RangeSpec exists.

---
 src/test/scala/chiselTests/RangeMacroTest.scala | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100644 src/test/scala/chiselTests/RangeMacroTest.scala

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
deleted file mode 100644
index cafff1d2..00000000
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ /dev/null
@@ -1,21 +0,0 @@
-// See LICENSE for license details.
-
-package chiselTests
-
-import chisel3._
-import scala.language.experimental.macros
-import org.scalatest._
-import org.scalatest.prop._
-import chisel3.testers.BasicTester
-
-
-/** Comprehensive test of static range parsing functionality.
-  * Note: negative (failure) conditions can't be tested because they will fail at compile time,
-  * before the testing environment is entered.
-  */
-class RangeMacroSpec extends ChiselPropSpec {
-  property("Range macros should work") {
-    range"(0,${1+1}]"
-    range"  (  0  ,  ${1+1}  ]  "
-  }
-}
-- 
cgit v1.2.3


From 87144822597c51fc010ab4aaca2db48904dce029 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Wed, 9 Nov 2016 16:57:26 -0800
Subject: Add some more tests.

---
 src/test/scala/chiselTests/RangeSpec.scala | 58 ++++++++++++++++++++++++++++--
 1 file changed, 56 insertions(+), 2 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index edaff8aa..b18e9d2a 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -8,10 +8,64 @@ import org.scalatest.{Matchers, FreeSpec}
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
     "to specify a UInt" in {
-      val x = UInt(range"[0, 7)")
+      val x = UInt(range"[0, 8)")
       x.getWidth should be (3)
 
       println(range"[4,32)")
+
+      UInt(range"[0, 8]").getWidth should be (4)
+    }
+
+    "to specify an SInt" in {
+      SInt(range"[0, 8)").getWidth should be (4)
+
+      SInt(range"[0, 8]").getWidth should be (5)
+
+      SInt(range"[-4, 4)").getWidth should be (3)
+    }
+
+    "it should check that the range is valid for UInt" in {
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"[1, 0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"[-1, 1]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"(0,0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"[0,0)")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"(0,0)")
+      }
+
+      UInt(range"[0, 0]").getWidth should be (1)
+    }
+
+    "it should check that the range is valid for SInt" in {
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"[1, 0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"(0,0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"[0,0)")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"(0,0)")
+      }
+
+      SInt(range"[0, 0]").getWidth should be (1)
     }
- }
+  }
 }
-- 
cgit v1.2.3


From 9192dc67a0a3b2abb1914ea5472c33c944908a80 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:04:17 -0800
Subject: Incorporate feedback.

---
 src/test/scala/chiselTests/RangeSpec.scala | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index b18e9d2a..8734c4d5 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -8,12 +8,11 @@ import org.scalatest.{Matchers, FreeSpec}
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
     "to specify a UInt" in {
-      val x = UInt(range"[0, 8)")
-      x.getWidth should be (3)
-
-      println(range"[4,32)")
+      UInt(range"[0, 8)").getWidth should be (3)
 
       UInt(range"[0, 8]").getWidth should be (4)
+
+      UInt(range"[0, 0]").getWidth should be (1)
     }
 
     "to specify an SInt" in {
@@ -22,6 +21,8 @@ class RangeSpec extends FreeSpec with Matchers {
       SInt(range"[0, 8]").getWidth should be (5)
 
       SInt(range"[-4, 4)").getWidth should be (3)
+
+      SInt(range"[0, 0]").getWidth should be (1)
     }
 
     "it should check that the range is valid for UInt" in {
@@ -44,8 +45,6 @@ class RangeSpec extends FreeSpec with Matchers {
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"(0,0)")
       }
-
-      UInt(range"[0, 0]").getWidth should be (1)
     }
 
     "it should check that the range is valid for SInt" in {
@@ -64,8 +63,6 @@ class RangeSpec extends FreeSpec with Matchers {
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"(0,0)")
       }
-
-      SInt(range"[0, 0]").getWidth should be (1)
     }
   }
 }
-- 
cgit v1.2.3


From 5499975f038eea469adfdd819d3727ea89686a39 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:13:14 -0800
Subject: Add a macro test case

---
 src/test/scala/chiselTests/RangeSpec.scala | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 8734c4d5..90189e0a 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -3,10 +3,33 @@
 package chiselTests
 
 import chisel3._
+import chisel3.internal.firrtl.{Open, Closed}
 import org.scalatest.{Matchers, FreeSpec}
 
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
+    "range macros should allow open and closed bounds" in {
+      {
+        val (lo, hi) = range"[-1, 1)"
+        lo should be (Closed(-1))
+        hi should be (Open(1))
+      }
+      {
+        val (lo, hi) = range"[-1, 1]"
+        lo should be (Closed(-1))
+        hi should be (Closed(1))
+      }
+      {
+        val (lo, hi) = range"(-1, 1]"
+        lo should be (Open(-1))
+        hi should be (Closed(1))
+      }
+      {
+        val (lo, hi) = range"(-1, 1)"
+        lo should be (Open(-1))
+        hi should be (Open(1))
+      }
+    }
     "to specify a UInt" in {
       UInt(range"[0, 8)").getWidth should be (3)
 
-- 
cgit v1.2.3


From 657befd9f948e54bf17f5d5f7fcacae96f93e86d Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:15:35 -0800
Subject: Change some of the test names.

---
 src/test/scala/chiselTests/RangeSpec.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 90189e0a..15b3092b 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -30,7 +30,7 @@ class RangeSpec extends FreeSpec with Matchers {
         hi should be (Open(1))
       }
     }
-    "to specify a UInt" in {
+    "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
 
       UInt(range"[0, 8]").getWidth should be (4)
@@ -38,7 +38,7 @@ class RangeSpec extends FreeSpec with Matchers {
       UInt(range"[0, 0]").getWidth should be (1)
     }
 
-    "to specify an SInt" in {
+    "SInt should get the correct width from a range" in {
       SInt(range"[0, 8)").getWidth should be (4)
 
       SInt(range"[0, 8]").getWidth should be (5)
@@ -48,7 +48,7 @@ class RangeSpec extends FreeSpec with Matchers {
       SInt(range"[0, 0]").getWidth should be (1)
     }
 
-    "it should check that the range is valid for UInt" in {
+    "UInt should check that the range is valid" in {
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[1, 0]")
       }
@@ -70,7 +70,7 @@ class RangeSpec extends FreeSpec with Matchers {
       }
     }
 
-    "it should check that the range is valid for SInt" in {
+    "SInt should check that the range is valid" in {
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"[1, 0]")
       }
-- 
cgit v1.2.3


From 02721d45f5261eac8d8eb6e260497a13aaa3692b Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:23:49 -0800
Subject: Add interpolated variables to range macro test.

---
 src/test/scala/chiselTests/RangeSpec.scala | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 15b3092b..25d963a1 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -30,6 +30,14 @@ class RangeSpec extends FreeSpec with Matchers {
         hi should be (Open(1))
       }
     }
+    "range macros should work with interpolated variables" in {
+      val a = 10
+      val b = -3
+
+      range"[$b, $a)" should be( (Closed(b), Open(a)) )
+
+      range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
+    }
     "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
 
-- 
cgit v1.2.3


From fdc61a258695d64b7716ae6bec6a37cabfb875bb Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:25:40 -0800
Subject: Write range macro tests in a better way.

---
 src/test/scala/chiselTests/RangeSpec.scala | 27 +++++++--------------------
 1 file changed, 7 insertions(+), 20 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 25d963a1..84db9b57 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -9,26 +9,13 @@ import org.scalatest.{Matchers, FreeSpec}
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
     "range macros should allow open and closed bounds" in {
-      {
-        val (lo, hi) = range"[-1, 1)"
-        lo should be (Closed(-1))
-        hi should be (Open(1))
-      }
-      {
-        val (lo, hi) = range"[-1, 1]"
-        lo should be (Closed(-1))
-        hi should be (Closed(1))
-      }
-      {
-        val (lo, hi) = range"(-1, 1]"
-        lo should be (Open(-1))
-        hi should be (Closed(1))
-      }
-      {
-        val (lo, hi) = range"(-1, 1)"
-        lo should be (Open(-1))
-        hi should be (Open(1))
-      }
+      range"[-1, 1)" should be( (Closed(-1), Open(1)) )
+
+      range"[-1, 1]" should be( (Closed(-1), Closed(1)) )
+
+      range"(-1, 1]" should be( (Open(-1), Closed(1)) )
+
+      range"(-1, 1)" should be( (Open(-1), Open(1)) )
     }
     "range macros should work with interpolated variables" in {
       val a = 10
-- 
cgit v1.2.3


From c9849a59d5ea0315096ff5f90db22ce39c7f4cc5 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:31:12 -0800
Subject: Oops, forgot to include literal expressions.

---
 src/test/scala/chiselTests/RangeSpec.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 84db9b57..509ed82e 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -24,6 +24,8 @@ class RangeSpec extends FreeSpec with Matchers {
       range"[$b, $a)" should be( (Closed(b), Open(a)) )
 
       range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
+
+      range"[${-3 - 7}, ${-3 + a})" should be( (Closed(-10), Open(-3 + a)) )
     }
     "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
-- 
cgit v1.2.3


From 2db9bc81015000b5ee4581dc57c0f339ae9f9329 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 14:15:37 -0800
Subject: Add invalid range specifier test

---
 src/test/scala/chiselTests/RangeSpec.scala | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 509ed82e..cbac4d4c 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -84,5 +84,18 @@ class RangeSpec extends FreeSpec with Matchers {
         SInt(range"(0,0)")
       }
     }
+
+    "Invalid range specifiers should fail at compile time" in {
+      assertDoesNotCompile(""" range"" """)
+      assertDoesNotCompile(""" range"[]" """)
+      assertDoesNotCompile(""" range"0" """)
+      assertDoesNotCompile(""" range"[0]" """)
+      assertDoesNotCompile(""" range"[0, 1" """)
+      assertDoesNotCompile(""" range"0, 1]" """)
+      assertDoesNotCompile(""" range"[0, 1, 2]" """)
+      assertDoesNotCompile(""" range"[a]" """)
+      assertDoesNotCompile(""" range"[a, b]" """)
+      assertCompiles(""" range"[0, 1]" """)  // syntax sanity check
+    }
   }
 }
-- 
cgit v1.2.3


From 876bc32feca6bd0a2aaec7019fd3d29675ce0255 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 15:23:36 -0800
Subject: Fix open-open range specifier, remove dead code, restyle tests

---
 src/test/scala/chiselTests/RangeSpec.scala | 58 +++++++++++++++---------------
 1 file changed, 28 insertions(+), 30 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index cbac4d4c..565d304d 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -8,40 +8,52 @@ import org.scalatest.{Matchers, FreeSpec}
 
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
+    "invalid range specifiers should fail at compile time" in {
+      assertDoesNotCompile(""" range"" """)
+      assertDoesNotCompile(""" range"[]" """)
+      assertDoesNotCompile(""" range"0" """)
+      assertDoesNotCompile(""" range"[0]" """)
+      assertDoesNotCompile(""" range"[0, 1" """)
+      assertDoesNotCompile(""" range"0, 1]" """)
+      assertDoesNotCompile(""" range"[0, 1, 2]" """)
+      assertDoesNotCompile(""" range"[a]" """)
+      assertDoesNotCompile(""" range"[a, b]" """)
+      assertCompiles(""" range"[0, 1]" """)  // syntax sanity check
+    }
+
     "range macros should allow open and closed bounds" in {
       range"[-1, 1)" should be( (Closed(-1), Open(1)) )
-
       range"[-1, 1]" should be( (Closed(-1), Closed(1)) )
-
       range"(-1, 1]" should be( (Open(-1), Closed(1)) )
-
       range"(-1, 1)" should be( (Open(-1), Open(1)) )
     }
+
+    "range specifiers should be whitespace tolerant" in {
+      range"[-1,1)" should be( (Closed(-1), Open(1)) )
+      range" [-1,1) " should be( (Closed(-1), Open(1)) )
+      range" [ -1 , 1 ) " should be( (Closed(-1), Open(1)) )
+      range"   [   -1   ,   1   )   " should be( (Closed(-1), Open(1)) )
+    }
+
     "range macros should work with interpolated variables" in {
       val a = 10
       val b = -3
 
       range"[$b, $a)" should be( (Closed(b), Open(a)) )
-
       range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
-
       range"[${-3 - 7}, ${-3 + a})" should be( (Closed(-10), Open(-3 + a)) )
     }
+
     "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
-
       UInt(range"[0, 8]").getWidth should be (4)
-
       UInt(range"[0, 0]").getWidth should be (1)
     }
 
     "SInt should get the correct width from a range" in {
       SInt(range"[0, 8)").getWidth should be (4)
-
       SInt(range"[0, 8]").getWidth should be (5)
-
       SInt(range"[-4, 4)").getWidth should be (3)
-
       SInt(range"[0, 0]").getWidth should be (1)
     }
 
@@ -49,53 +61,39 @@ class RangeSpec extends FreeSpec with Matchers {
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[1, 0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[-1, 1]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"(0,0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[0,0)")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"(0,0)")
       }
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"(0,1)")
+      }
     }
 
     "SInt should check that the range is valid" in {
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"[1, 0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"(0,0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"[0,0)")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"(0,0)")
       }
-    }
-
-    "Invalid range specifiers should fail at compile time" in {
-      assertDoesNotCompile(""" range"" """)
-      assertDoesNotCompile(""" range"[]" """)
-      assertDoesNotCompile(""" range"0" """)
-      assertDoesNotCompile(""" range"[0]" """)
-      assertDoesNotCompile(""" range"[0, 1" """)
-      assertDoesNotCompile(""" range"0, 1]" """)
-      assertDoesNotCompile(""" range"[0, 1, 2]" """)
-      assertDoesNotCompile(""" range"[a]" """)
-      assertDoesNotCompile(""" range"[a, b]" """)
-      assertCompiles(""" range"[0, 1]" """)  // syntax sanity check
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"(0,1)")
+      }
     }
   }
 }
-- 
cgit v1.2.3


From fffde2bfbffeacbe9cca68d539b199bd18e30294 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 16:35:06 -0800
Subject: Address review comments

---
 src/test/scala/chiselTests/RangeSpec.scala | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 565d304d..60ececbe 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -42,6 +42,9 @@ class RangeSpec extends FreeSpec with Matchers {
       range"[$b, $a)" should be( (Closed(b), Open(a)) )
       range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
       range"[${-3 - 7}, ${-3 + a})" should be( (Closed(-10), Open(-3 + a)) )
+
+      def number(n: Int): Int = n
+      range"[${number(1)}, ${number(3)})" should be( (Closed(1), Open(3)) )
     }
 
     "UInt should get the correct width from a range" in {
-- 
cgit v1.2.3


From e8aea3f4153b58321784ac33734305207570ef75 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 17:51:56 -0800
Subject: Move ChiselRange to experimental

---
 src/test/scala/chiselTests/RangeSpec.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 60ececbe..e2313f34 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -3,6 +3,8 @@
 package chiselTests
 
 import chisel3._
+import chisel3.experimental.ChiselRange
+
 import chisel3.internal.firrtl.{Open, Closed}
 import org.scalatest.{Matchers, FreeSpec}
 
-- 
cgit v1.2.3


From b0cc0c93a80aec5bed54cfb11923636c09b7e180 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:21:59 -0800
Subject: SInt conversion finished, everything builds again

---
 src/test/scala/chiselTests/AnnotatingExample.scala | 22 +++++++++++-----------
 src/test/scala/chiselTests/DriverSpec.scala        |  4 ++--
 2 files changed, 13 insertions(+), 13 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala
index 04228d6b..0be3ba59 100644
--- a/src/test/scala/chiselTests/AnnotatingExample.scala
+++ b/src/test/scala/chiselTests/AnnotatingExample.scala
@@ -24,8 +24,8 @@ import scala.util.DynamicVariable
 
 class SomeSubMod(param1: Int, param2: Int) extends Module {
   val io = new Bundle {
-    val in = UInt(INPUT, 16)
-    val out = SInt(OUTPUT, 32)
+    val in = Input(UInt(16.W))
+    val out = Output(SInt(32.W))
   }
   val annotate = MyBuilder.myDynamicContext.annotationMap
 
@@ -36,18 +36,18 @@ class SomeSubMod(param1: Int, param2: Int) extends Module {
 
 class AnnotatingExample extends Module {
   val io = new Bundle {
-    val a  = UInt(INPUT, 32)
-    val b  = UInt(INPUT, 32)
-    val e  = Bool(INPUT)
-    val z  = UInt(OUTPUT, 32)
-    val v  = Bool(OUTPUT)
+    val a  = Input(UInt(32.W))
+    val b  = Input(UInt(32.W))
+    val e  = Input(Bool())
+    val z  = Output(UInt(32.W))
+    val v  = Output(Bool())
     val bun = new Bundle {
-      val nested_1 = UInt(INPUT, 12)
-      val nested_2 = Bool(OUTPUT)
+      val nested_1 = Input(UInt(12.W))
+      val nested_2 = Output(Bool())
     }
   }
-  val x = Reg(UInt(width = 32))
-  val y = Reg(UInt(width = 32))
+  val x = Reg(UInt(32.W))
+  val y = Reg(UInt(32.W))
 
   val subModule1 = Module(new SomeSubMod(1, 2))
   val subModule2 = Module(new SomeSubMod(3, 4))
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index 4f9619e3..d77dbaf1 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -8,8 +8,8 @@ import org.scalatest.{Matchers, FreeSpec}
 
 class DummyModule extends Module {
   val io = IO(new Bundle {
-    val in = UInt(INPUT, 1)
-    val out = UInt(OUTPUT, 1)
+    val in = Input(UInt(1.W))
+    val out = Output(UInt(1.W))
   })
   io.out := io.in
 }
-- 
cgit v1.2.3


From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 src/test/scala/chiselTests/Assert.scala            |  8 ++--
 src/test/scala/chiselTests/BetterNamingTests.scala |  4 +-
 src/test/scala/chiselTests/BlackBox.scala          | 46 +++++++++----------
 src/test/scala/chiselTests/BundleWire.scala        | 20 ++++-----
 src/test/scala/chiselTests/Clock.scala             |  2 +-
 .../scala/chiselTests/CompileOptionsTest.scala     | 52 +++++++++++-----------
 src/test/scala/chiselTests/ComplexAssign.scala     | 20 ++++-----
 src/test/scala/chiselTests/Counter.scala           |  8 ++--
 src/test/scala/chiselTests/Decoder.scala           |  8 ++--
 src/test/scala/chiselTests/Direction.scala         |  8 ++--
 .../scala/chiselTests/EnableShiftRegister.scala    | 12 ++---
 src/test/scala/chiselTests/GCD.scala               | 12 ++---
 src/test/scala/chiselTests/IOCompatibility.scala   | 10 ++---
 src/test/scala/chiselTests/LFSR16.scala            |  4 +-
 src/test/scala/chiselTests/MemorySearch.scala      | 14 +++---
 src/test/scala/chiselTests/Module.scala            |  8 ++--
 .../chiselTests/ModuleExplicitResetSpec.scala      | 10 ++---
 src/test/scala/chiselTests/MulLookup.scala         |  8 ++--
 src/test/scala/chiselTests/MultiAssign.scala       |  4 +-
 src/test/scala/chiselTests/OptionBundle.scala      |  8 ++--
 src/test/scala/chiselTests/Padding.scala           |  6 +--
 .../scala/chiselTests/ParameterizedModule.scala    |  8 ++--
 src/test/scala/chiselTests/PrintableSpec.scala     | 26 +++++------
 src/test/scala/chiselTests/Printf.scala            |  6 +--
 src/test/scala/chiselTests/Reg.scala               | 10 ++---
 src/test/scala/chiselTests/Risc.scala              | 22 ++++-----
 src/test/scala/chiselTests/SIntOps.scala           | 26 +++++------
 src/test/scala/chiselTests/Stack.scala             | 20 ++++-----
 src/test/scala/chiselTests/Tbl.scala               | 20 ++++-----
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  4 +-
 src/test/scala/chiselTests/UIntOps.scala           | 26 +++++------
 src/test/scala/chiselTests/Vec.scala               |  8 ++--
 src/test/scala/chiselTests/VectorPacketIO.scala    |  2 +-
 src/test/scala/chiselTests/VendingMachine.scala    |  2 +-
 src/test/scala/chiselTests/When.scala              | 48 ++++++++++----------
 src/test/scala/cookbook/Bundle2UInt.scala          | 10 ++---
 src/test/scala/cookbook/CookbookSpec.scala         |  2 +-
 src/test/scala/cookbook/UInt2Bundle.scala          | 10 ++---
 src/test/scala/cookbook/UInt2VecOfBool.scala       | 10 ++---
 src/test/scala/cookbook/VecOfBool2UInt.scala       |  4 +-
 40 files changed, 268 insertions(+), 268 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index efc2e1e7..475e18f7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -8,7 +8,7 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class FailingAssertTester() extends BasicTester {
-  assert(Bool(false))
+  assert(false.B)
   // Wait to come out of reset
   val (_, done) = Counter(!reset, 4)
   when (done) {
@@ -17,7 +17,7 @@ class FailingAssertTester() extends BasicTester {
 }
 
 class SucceedingAssertTester() extends BasicTester {
-  assert(Bool(true))
+  assert(true.B)
   // Wait to come out of reset
   val (_, done) = Counter(!reset, 4)
   when (done) {
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt(0xbeef))
-  val b = Reg(init = UInt(0xbeef))
+  val a = Reg(init = 0xbeef.U)
+  val b = Reg(init = 0xbeef.U)
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index f5872adb..df23f0a2 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -9,14 +9,14 @@ import chisel3.util._
 // Defined outside of the class so we don't get $ in name
 class Other(w: Int) extends Module {
   val io = new Bundle {
-    val a = UInt(width = w)
+    val a = UInt(w.W)
   }
 }
 class PerNameIndexing(count: Int) extends Module {
   val io = new Bundle { }
 
   val wires = Seq.tabulate(count) { i => Module(new Other(i)) }
-  val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(width = i), 16)) }
+  val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(i.W), 16)) }
 }
 
 // Note this only checks Iterable[Chisel.Data] which excludes Maps
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index d8821134..8b4cf157 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -37,11 +37,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt(1)
-  blackBoxNeg.io.in := UInt(0)
+  blackBoxPos.io.in := 1.U
+  blackBoxNeg.io.in := 0.U
 
-  assert(blackBoxNeg.io.out === UInt(1))
-  assert(blackBoxPos.io.out === UInt(0))
+  assert(blackBoxNeg.io.out === 1.U)
+  assert(blackBoxPos.io.out === 0.U)
   stop()
 }
 
@@ -56,15 +56,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt(1)
-  blackBoxInvNeg.io.in := UInt(0)
-  blackBoxPassPos.io.in := UInt(1)
-  blackBoxPassNeg.io.in := UInt(0)
+  blackBoxInvPos.io.in := 1.U
+  blackBoxInvNeg.io.in := 0.U
+  blackBoxPassPos.io.in := 1.U
+  blackBoxPassNeg.io.in := 0.U
 
-  assert(blackBoxInvNeg.io.out === UInt(1))
-  assert(blackBoxInvPos.io.out === UInt(0))
-  assert(blackBoxPassNeg.io.out === UInt(0))
-  assert(blackBoxPassPos.io.out === UInt(1))
+  assert(blackBoxInvNeg.io.out === 1.U)
+  assert(blackBoxInvPos.io.out === 0.U)
+  assert(blackBoxPassNeg.io.out === 0.U)
+  assert(blackBoxPassPos.io.out === 1.U)
   stop()
 }
 
@@ -72,14 +72,14 @@ class BlackBoxWithClockTester extends BasicTester {
   val blackBox = Module(new BlackBoxRegister)
   val model = Reg(Bool())
 
-  val (cycles, end) = Counter(Bool(true), 15)
+  val (cycles, end) = Counter(true.B, 15)
 
   val impetus = cycles(0)
   blackBox.io.clock := clock
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt(0)) {
+  when(cycles > 0.U) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -121,16 +121,16 @@ class BlackBoxWithParamsTester extends BasicTester {
   val blackBoxTypeParamBit = Module(new BlackBoxTypeParam(1, "bit"))
   val blackBoxTypeParamWord = Module(new BlackBoxTypeParam(32, "bit [31:0]"))
 
-  val (cycles, end) = Counter(Bool(true), 4)
+  val (cycles, end) = Counter(true.B, 4)
 
-  assert(blackBoxOne.io.out  === UInt(1))
-  assert(blackBoxFour.io.out === UInt(4))
-  assert(blackBoxStringParamOne.io.out === UInt(1))
-  assert(blackBoxStringParamTwo.io.out === UInt(2))
-  assert(blackBoxRealParamOne.io.out === UInt(0x3ff0000000000000L))
-  assert(blackBoxRealParamNeg.io.out === UInt(BigInt("bff0000000000000", 16)))
-  assert(blackBoxTypeParamBit.io.out === UInt(1))
-  assert(blackBoxTypeParamWord.io.out === UInt("hdeadbeef", 32))
+  assert(blackBoxOne.io.out  === 1.U)
+  assert(blackBoxFour.io.out === 4.U)
+  assert(blackBoxStringParamOne.io.out === 1.U)
+  assert(blackBoxStringParamTwo.io.out === 2.U)
+  assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U)
+  assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U)
+  assert(blackBoxTypeParamBit.io.out === 1.U)
+  assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 5b38ff6e..0faab9d0 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -8,8 +8,8 @@ import chisel3.testers.BasicTester
 //import chisel3.core.ExplicitCompileOptions.Strict
 
 class Coord extends Bundle {
-  val x = UInt.width( 32)
-  val y = UInt.width( 32)
+  val x = UInt(32.W)
+  val y = UInt(32.W)
 }
 
 class BundleWire(n: Int) extends Module {
@@ -26,12 +26,12 @@ class BundleWire(n: Int) extends Module {
 
 class BundleToUnitTester extends BasicTester {
   val bundle1 = Wire(new Bundle {
-    val a = UInt(width = 4)
-    val b = UInt(width = 4)
+    val a = UInt(4.W)
+    val b = UInt(4.W)
   })
   val bundle2 = Wire(new Bundle {
-    val a = UInt(width = 2)
-    val b = UInt(width = 6)
+    val a = UInt(2.W)
+    val b = UInt(6.W)
   })
 
   // 0b00011011 split as 0001 1011 and as 00 011011
@@ -47,11 +47,11 @@ class BundleToUnitTester extends BasicTester {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt(x)
-  dut.io.in.y := UInt(y)
+  dut.io.in.x := x.asUInt
+  dut.io.in.y := y.asUInt
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt(x))
-    assert(elt.y === UInt(y))
+    assert(elt.x === x.asUInt)
+    assert(elt.y === y.asUInt)
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
index 79dd2de4..78d60ed2 100644
--- a/src/test/scala/chiselTests/Clock.scala
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -10,7 +10,7 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class ClockAsUIntTester extends BasicTester {
-  assert(Bool(true).asClock.asUInt === UInt(1))
+  assert(true.B.asClock.asUInt === 1.U)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 57ceff3f..cc0a966c 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -27,12 +27,12 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   class SmallBundle extends Bundle {
-    val f1 = UInt(width = 4)
-    val f2 = UInt(width = 5)
+    val f1 = UInt(4.W)
+    val f2 = UInt(5.W)
     override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type]
   }
   class BigBundle extends SmallBundle {
-    val f3 = UInt(width = 6)
+    val f3 = UInt(6.W)
     override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
   }
 
@@ -73,7 +73,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
           val in = Input(new SmallBundle)
           val out = Output(new BigBundle)
         })
-        val badReg = Reg(UInt(7, width=4))
+        val badReg = Reg(7.U(4.W))
       }
       elaborate { new CreateRegFromBoundTypeModule() }
     }
@@ -87,7 +87,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val in = Input(new SmallBundle)
         val out = Output(new BigBundle)
       })
-      val badReg = Reg(UInt(7, width=4))
+      val badReg = Reg(7.U(4.W))
     }
     elaborate { new CreateRegFromBoundTypeModule() }
   }
@@ -97,7 +97,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       })
       io.out := io.in(1)
@@ -110,7 +110,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       }
       io.out := io.in(1)
@@ -124,7 +124,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
-          val in = UInt(width = 32).asInput
+          val in = UInt(32.W).asInput
           val out = Bool().asOutput
         }
         io.out := io.in(1)
@@ -141,8 +141,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
-          val in = Input(UInt(width = 3))
-          val out = Output(UInt(width = 4))
+          val in = Input(UInt(3.W))
+          val out = Output(UInt(4.W))
         })
       }
       class SwappedConnectionModule extends SimpleModule {
@@ -158,8 +158,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
-        val in = Input(UInt(width = 3))
-        val out = Output(UInt(width = 4))
+        val in = Input(UInt(3.W))
+        val out = Output(UInt(4.W))
       })
     }
     class SwappedConnectionModule extends SimpleModule {
@@ -177,15 +177,15 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
-          val in = Input(UInt(width = 3))
-          val out = Output(UInt(width = 4))
+          val in = Input(UInt(3.W))
+          val out = Output(UInt(4.W))
         })
-        val noDir = Wire(UInt(width = 3))
+        val noDir = Wire(UInt(3.W))
       }
 
       class DirectionLessConnectionModule extends SimpleModule {
-        val a = UInt(0, width = 3)
-        val b = Wire(UInt(width = 3))
+        val a = 0.U(3.W)
+        val b = Wire(UInt(3.W))
         val child = Module(new SimpleModule)
         b := child.noDir
       }
@@ -198,15 +198,15 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
-        val in = Input(UInt(width = 3))
-        val out = Output(UInt(width = 4))
+        val in = Input(UInt(3.W))
+        val out = Output(UInt(4.W))
       })
-      val noDir = Wire(UInt(width = 3))
+      val noDir = Wire(UInt(3.W))
     }
 
     class DirectionLessConnectionModule extends SimpleModule {
-      val a = UInt(0, width = 3)
-      val b = Wire(UInt(width = 3))
+      val a = 0.U(3.W)
+      val b = Wire(UInt(3.W))
       val child = Module(new SimpleModule)
       b := child.noDir
     }
@@ -217,7 +217,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends StrictModule {
       val io = IO(new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       })
       io.out := io.in(1)
@@ -231,7 +231,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends NotStrictModule {
       val io = new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       }
       io.out := io.in(1)
@@ -246,7 +246,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       implicit val strictWithoutIOWrap = StrictWithoutIOWrap
       class RequireIOWrapModule extends StrictModule {
         val io = new Bundle {
-          val in = UInt(width = 32).asInput
+          val in = UInt(32.W).asInput
           val out = Bool().asOutput
         }
         io.out := io.in(1)
@@ -274,7 +274,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
     class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) {
       val io = new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       }
     }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index c5a23f82..f7484501 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -17,28 +17,28 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
 class ComplexAssign(w: Int) extends Module {
   val io = IO(new Bundle {
     val e   = Input(Bool())
-    val in  = Input(new Complex(UInt.width(w), UInt.width(w)))
-    val out = Output(new Complex(UInt.width(w), UInt.width(w)))
+    val in  = Input(new Complex(UInt(w.W), UInt(w.W)))
+    val out = Output(new Complex(UInt(w.W), UInt(w.W)))
   })
   when (io.e) {
-    val tmp = Wire(new Complex(UInt.width(w), UInt.width(w)))
+    val tmp = Wire(new Complex(UInt(w.W), UInt(w.W)))
     tmp := io.in
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt(0)
-    io.out.im := UInt(0)
+    io.out.re := 0.U
+    io.out.im := 0.U
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), enList.size)
+  val (cnt, wrap) = Counter(true.B, enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt(re)
-  dut.io.in.im := UInt(im)
+  dut.io.in.re := re.asUInt
+  dut.io.in.im := im.asUInt
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, 0.U)
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, 0.U)
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 69d8a44a..cccd8c0e 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -11,18 +11,18 @@ import chisel3.util._
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
-  when(Bool(true)) { cnt.inc() }
+  when(true.B) { cnt.inc() }
   when(cnt.value === UInt(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt(seed))
+  val ens = Reg(init = seed.asUInt)
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
-  val (_, done) = Counter(Bool(true), 33)
+  val (_, done) = Counter(true.B, 33)
 
   when(done) {
     assert(cntEnVal === UInt(popCount(seed)))
@@ -31,7 +31,7 @@ class EnableTester(seed: Int) extends BasicTester {
 }
 
 class WrapTester(max: Int) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), max)
+  val (cnt, wrap) = Counter(true.B, max)
   when(wrap) {
     assert(cnt === UInt(max - 1))
     stop()
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index b50a80c0..ff73a676 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
-    val inst  = Input(UInt.width(32))
+    val inst  = Input(UInt(32.W))
     val matched = Output(Bool())
   })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
@@ -20,11 +20,11 @@ class Decoder(bitpats: List[String]) extends Module {
 
 class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val (insts, bitpats) = pairs.unzip
-  val (cnt, wrap) = Counter(Bool(true), pairs.size)
+  val (cnt, wrap) = Counter(true.B, pairs.size)
   val dut = Module(new Decoder(bitpats))
-  dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
+  dut.io.inst := Vec(insts.map(_.asUInt))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt(0))
+    assert(cnt === 0.U)
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 949b92ed..c3400013 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -9,17 +9,17 @@ import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
-    val in = Input(UInt.width(32))
-    val out = Output(UInt.width(32))
+    val in = Input(UInt(32.W))
+    val out = Output(UInt(32.W))
   })
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt(0)
+  io.out := 0.U
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt(0)
+  io.in := 0.U
 }
 
 class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f3e0dd1..6dc4aac6 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,14 +6,14 @@ import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt.width(4))
+    val in    = Input(UInt(4.W))
     val shift = Input(Bool())
-    val out   = Output(UInt.width(4))
+    val out   = Output(UInt(4.W))
   })
-  val r0 = Reg(init = UInt(0, 4))
-  val r1 = Reg(init = UInt(0, 4))
-  val r2 = Reg(init = UInt(0, 4))
-  val r3 = Reg(init = UInt(0, 4))
+  val r0 = Reg(init = 0.U(4.W))
+  val r1 = Reg(init = 0.U(4.W))
+  val r2 = Reg(init = 0.U(4.W))
+  val r3 = Reg(init = 0.U(4.W))
   when(io.shift) {
     r0 := io.in
     r1 := r0
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d683ce34..c20d26ad 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -9,14 +9,14 @@ import org.scalatest.prop._
 
 class GCD extends Module {
   val io = IO(new Bundle {
-    val a  = Input(UInt.width(32))
-    val b  = Input(UInt.width(32))
+    val a  = Input(UInt(32.W))
+    val b  = Input(UInt(32.W))
     val e  = Input(Bool())
-    val z  = Output(UInt.width(32))
+    val z  = Output(UInt(32.W))
     val v  = Output(Bool())
   })
-  val x = Reg(UInt.width( 32))
-  val y = Reg(UInt.width( 32))
+  val x = Reg(UInt(32.W))
+  val y = Reg(UInt(32.W))
   when (x > y)   { x := x -% y }
   .otherwise     { y := y -% x }
   when (io.e) { x := io.a; y := io.b }
@@ -30,7 +30,7 @@ class GCDTester(a: Int, b: Int, z: Int) extends BasicTester {
   dut.io.a := a.U
   dut.io.b := b.U
   dut.io.e := first
-  when(first) { first := Bool(false) }
+  when(first) { first := false.B }
   when(!first && dut.io.v) {
     assert(dut.io.z === z.U)
     stop()
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 552fe776..521e895d 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -7,19 +7,19 @@ import chisel3.core.Binding.BindingException
 import org.scalatest._
 
 class IOCSimpleIO extends Bundle {
-  val in  = Input(UInt(width=32))
-  val out = Output(UInt(width=32))
+  val in  = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
 }
 
 class IOCPlusOne extends Module {
   val io = IO(new IOCSimpleIO)
-  io.out := io.in + UInt(1)
+  io.out := io.in + 1.U
 }
 
 class IOCModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Vec(n, Input(UInt(width=32)))
-    val outs = Vec(n, Output(UInt(width=32)))
+    val ins  = Vec(n, Input(UInt(32.W)))
+    val outs = Vec(n, Output(UInt(32.W)))
   })
   val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index b13b67e3..09beddb9 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -9,9 +9,9 @@ import chisel3.util._
 class LFSR16 extends Module {
   val io = IO(new Bundle {
     val inc = Input(Bool())
-    val out = Output(UInt.width(16))
+    val out = Output(UInt(16.W))
   })
-  val res = Reg(init = UInt(1, 16))
+  val res = Reg(init = 1.U(16.W))
   when (io.inc) {
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
     res := nxt_res
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 1d09f3c5..befbf010 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,21 +7,21 @@ import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
-    val target  = Input(UInt.width(4))
+    val target  = Input(UInt(4.W))
     val en      = Input(Bool())
     val done    = Output(Bool())
-    val address = Output(UInt.width(3))
+    val address = Output(UInt(3.W))
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
-  val index = Reg(init = UInt(0, width = 3))
+  val index = Reg(init = 0.U(3.W))
   val elts  = Vec(vals.map(UInt(_,4)))
-  // val elts  = Mem(UInt(width = 32), 8) TODO ????
+  // val elts  = Mem(UInt(32.W), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
+  val end  = !io.en && ((elt === io.target) || (index === 7.U))
   when (io.en) {
-    index := UInt(0)
+    index := 0.U
   } .elsewhen (!end) {
-    index := index +% UInt(1)
+    index := index +% 1.U
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index c902d073..4f043f0a 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,8 +5,8 @@ package chiselTests
 import chisel3._
 
 class SimpleIO extends Bundle {
-  val in  = Input(UInt.width(32))
-  val out = Output(UInt.width(32))
+  val in  = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
 }
 
 class PlusOne extends Module {
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt(32)))
-    val outs = Output(Vec(n, UInt(32)))
+    val ins  = Input(Vec(n, 32.U))
+    val outs = Output(Vec(n, 32.U))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
index f8206b9c..27cf4a5f 100644
--- a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
+++ b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
@@ -6,13 +6,13 @@ class ModuleExplicitResetSpec extends ChiselFlatSpec  {
 
   "A Module with an explicit reset in compatibility mode" should "elaborate" in {
     import Chisel._
-    val myReset = Bool(true)
+    val myReset = true.B
     class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
       val io = new Bundle {
         val done = Bool(OUTPUT)
       }
 
-      io.done := Bool(false)
+      io.done := false.B
     }
 
     elaborate {
@@ -22,13 +22,13 @@ class ModuleExplicitResetSpec extends ChiselFlatSpec  {
 
   "A Module with an explicit reset in non-compatibility mode" should "elaborate" in {
     import chisel3._
-    val myReset = Bool(true)
+    val myReset = true.B
     class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
       val io = IO(new Bundle {
-        val done = Bool(OUTPUT)
+        val done = Output(Bool())
       })
 
-      io.done := Bool(false)
+      io.done := false.B
     }
 
     elaborate {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 26ee4e03..f0b2aa21 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -9,8 +9,8 @@ import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
-    val x   = Input(UInt.width(w))
-    val y   = Input(UInt.width(w))
+    val x   = Input(UInt(w.W))
+    val y   = Input(UInt(w.W))
     val z   = Output(UInt.width(2 * w))
   })
   val tbl = Vec(
@@ -24,8 +24,8 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt(x)
-  dut.io.y := UInt(y)
+  dut.io.x := x.asUInt
+  dut.io.y := y.asUInt
   assert(dut.io.z === UInt(x * y))
   stop()
 }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 397ea4c2..fbe57da5 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,10 +9,10 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
-  val countOnClockCycles = Bool(true)
+  val countOnClockCycles = true.B
   val (cnt, wrap) = Counter(countOnClockCycles,2)
 
-  val test = Wire(UInt.width(4))
+  val test = Wire(UInt(4.W))
   assert(test === 7.U)  // allow read references before assign references
 
   test := 13.U
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index 8e4c7579..d1b9152d 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -20,7 +20,7 @@ class OptionBundleModule(hasIn: Boolean) extends Module {
   if (hasIn) {
     io.out := io.in.get
   } else {
-    io.out := Bool(false)
+    io.out := false.B
   }
 }
 
@@ -33,14 +33,14 @@ class SomeOptionBundleTester(expected: Boolean) extends BasicTester {
 
 class NoneOptionBundleTester() extends BasicTester {
   val mod = Module(new OptionBundleModule(false))
-  assert(mod.io.out === Bool(false))
+  assert(mod.io.out === false.B)
   stop()
 }
 
 class InvalidOptionBundleTester() extends BasicTester {
   val mod = Module(new OptionBundleModule(false))
-  mod.io.in.get := Bool(true)
-  assert(Bool(false))
+  mod.io.in.get := true.B
+  assert(false.B)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 42df6802..6f256b64 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -6,9 +6,9 @@ import chisel3._
 
 class Padder extends Module {
   val io = IO(new Bundle {
-    val a   = Input(UInt.width(4))
-    val asp = Output(SInt.width(8))
-    val aup = Output(UInt.width(8))
+    val a   = Input(UInt(4.W))
+    val asp = Output(SInt(8.W))
+    val aup = Output(UInt(8.W))
   })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 14b21631..028b5baf 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -26,10 +26,10 @@ class ParameterizedModuleTester() extends BasicTester {
   val invert = Module(new ParameterizedModule(true))
   val noninvert = Module(new ParameterizedModule(false))
 
-  invert.io.in := Bool(true)
-  noninvert.io.in := Bool(true)
-  assert(invert.io.out === Bool(false))
-  assert(noninvert.io.out === Bool(true))
+  invert.io.in := true.B
+  noninvert.io.in := true.B
+  assert(invert.io.out === false.B)
+  assert(noninvert.io.out === true.B)
 
   stop()
 }
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 12564a40..62784cff 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -67,7 +67,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "generate proper printf for simple Decimal printing" in {
     class MyModule extends BasicTester {
-      val myWire = Wire(init = UInt(1234))
+      val myWire = Wire(init = 1234.U)
       printf(p"myWire = ${Decimal(myWire)}")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -78,7 +78,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "handle printing literals" in {
     class MyModule extends BasicTester {
-      printf(Decimal(UInt(10, 32)))
+      printf(Decimal(10.U(32.W)))
     }
     val firrtl = Driver.emit(() => new MyModule)
     getPrintfs(firrtl) match {
@@ -102,11 +102,11 @@ class PrintableSpec extends FlatSpec with Matchers {
     // parent module
     class MySubModule extends Module {
       val io = new Bundle {
-        val fizz = UInt(width = 32)
+        val fizz = UInt(32.W)
       }
     }
     class MyBundle extends Bundle {
-      val foo = UInt(width = 32)
+      val foo = UInt(32.W)
       override def cloneType = (new MyBundle).asInstanceOf[this.type]
     }
     class MyModule extends BasicTester {
@@ -129,7 +129,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   it should "handle printing ports of submodules" in {
     class MySubModule extends Module {
       val io = new Bundle {
-        val fizz = UInt(width = 32)
+        val fizz = UInt(32.W)
       }
     }
     class MyModule extends BasicTester {
@@ -144,8 +144,8 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "print UInts and SInts as Decimal by default" in {
     class MyModule extends BasicTester {
-      val myUInt = Wire(init = UInt(0))
-      val mySInt = Wire(init = SInt(-1))
+      val myUInt = Wire(init = 0.U)
+      val mySInt = Wire(init = -1.S)
       printf(p"$myUInt & $mySInt")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -156,8 +156,8 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "print Vecs like Scala Seqs by default" in {
     class MyModule extends BasicTester {
-      val myVec = Wire(Vec(4, UInt(width = 32)))
-      myVec foreach (_ := UInt(0))
+      val myVec = Wire(Vec(4, UInt(32.W)))
+      myVec foreach (_ := 0.U)
       printf(p"$myVec")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -170,11 +170,11 @@ class PrintableSpec extends FlatSpec with Matchers {
   it should "print Bundles like Scala Maps by default" in {
     class MyModule extends BasicTester {
       val myBun = Wire(new Bundle {
-        val foo = UInt(width = 32)
-        val bar = UInt(width = 32)
+        val foo = UInt(32.W)
+        val bar = UInt(32.W)
       })
-      myBun.foo := UInt(0)
-      myBun.bar := UInt(0)
+      myBun.foo := 0.U
+      myBun.bar := 0.U
       printf(p"$myBun")
     }
     val firrtl = Driver.emit(() => new MyModule)
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 28b6132b..6a0569a2 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt(254)
+  val x = 254.U
   printf("x=%x", x)
   stop()
 }
@@ -19,8 +19,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt(254)
-  val y = UInt(255)
+  val x = 254.U
+  val y = 255.U
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 90992c01..43e64fe7 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -17,7 +17,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      val reg = Reg(t=UInt(2.W), next=Wire(UInt(3.W)), init=20.U)
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
@@ -25,13 +25,13 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20))
+      val reg1 = Reg(next=Wire(UInt(3.W)), init=20.U)
       reg1.isWidthKnown should be (false)
       DataMirror.widthOf(reg1).known should be (false)
-      val reg2 = Reg(init=UInt(20))
+      val reg2 = Reg(init=20.U)
       reg2.isWidthKnown should be (false)
       DataMirror.widthOf(reg2).known should be (false)
-      val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5))
+      val reg3 = Reg(next=Wire(UInt(3.W)), init=5.U)
       reg3.isWidthKnown should be (false)
       DataMirror.widthOf(reg3).known should be (false)
     }
@@ -40,7 +40,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
     class RegForcedWidthTester extends BasicTester {
-      val reg2 = Reg(init=UInt(20, width=7))
+      val reg2 = Reg(init=20.U(7.W))
       reg2.getWidth should be (7)
     }
     elaborate{ new RegForcedWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 6d5a0a76..ae99df59 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,18 +8,18 @@ import chisel3.util._
 class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
-    val wrAddr = Input(UInt.width(8))
-    val wrData = Input(Bits.width(32))
+    val wrAddr = Input(UInt(8.W))
+    val wrData = Input(Bits(32.W))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
-    val out    = Output(Bits.width(32))
+    val out    = Output(Bits(32.W))
   })
   val memSize = 256
-  val file = Mem(memSize, Bits.width(32))
-  val code = Mem(memSize, Bits.width(32))
-  val pc   = Reg(init=UInt(0, 8))
+  val file = Mem(memSize, Bits(32.W))
+  val code = Mem(memSize, Bits(32.W))
+  val pc   = Reg(init=0.U(8.W))
 
-  val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2)
+  val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2)
 
   val inst = code(pc)
   val op   = inst(31,24)
@@ -29,16 +29,16 @@ class Risc extends Module {
 
   val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
   val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
-  val rc = Wire(Bits.width(32))
+  val rc = Wire(Bits(32.W))
 
-  io.valid := Bool(false)
+  io.valid := false.B
   io.out   := 0.asUInt()
   rc       := 0.asUInt()
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt(0)
+    pc := 0.U
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
@@ -46,7 +46,7 @@ class Risc extends Module {
     }
     io.out := rc
     when (rci === 255.asUInt()) {
-      io.valid := Bool(true)
+      io.valid := true.B
     } .otherwise {
       file(rci) := rc
     }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 392c4803..900eb074 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -7,22 +7,22 @@ import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(SInt.width(16))
-    val b = Input(SInt.width(16))
-    val addout = Output(SInt.width(16))
-    val subout = Output(SInt.width(16))
-    val timesout = Output(SInt.width(16))
-    val divout = Output(SInt.width(16))
-    val modout = Output(SInt.width(16))
-    val lshiftout = Output(SInt.width(16))
-    val rshiftout = Output(SInt.width(16))
+    val a = Input(SInt(16.W))
+    val b = Input(SInt(16.W))
+    val addout = Output(SInt(16.W))
+    val subout = Output(SInt(16.W))
+    val timesout = Output(SInt(16.W))
+    val divout = Output(SInt(16.W))
+    val modout = Output(SInt(16.W))
+    val lshiftout = Output(SInt(16.W))
+    val rshiftout = Output(SInt(16.W))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
     val noteqout = Output(Bool())
     val lesseqout = Output(Bool())
     val greateqout = Output(Bool())
-    val negout = Output(SInt.width(16))
+    val negout = Output(SInt(16.W))
   })
 
   val a = io.a
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
+  //io.divout := a / Mux(b === 0.S, 1.S, b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt(0)
+  //io.modout := 0.S
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt(0) -% a)
+  io.negout := (0.S -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index a72af928..ce8fd9fc 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -12,23 +12,23 @@ class ChiselStack(val depth: Int) extends Module {
     val push    = Input(Bool())
     val pop     = Input(Bool())
     val en      = Input(Bool())
-    val dataIn  = Input(UInt.width(32))
-    val dataOut = Output(UInt.width(32))
+    val dataIn  = Input(UInt(32.W))
+    val dataOut = Output(UInt(32.W))
   })
 
-  val stack_mem = Mem(depth, UInt.width(32))
+  val stack_mem = Mem(depth, UInt(32.W))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
-  val out       = Reg(init = UInt(0, width = 32))
+  val out       = Reg(init = 0.U(32.W))
 
   when (io.en) {
-    when(io.push && (sp < UInt(depth))) {
+    when(io.push && (sp < depth.asUInt)) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt(1)
-    } .elsewhen(io.pop && (sp > UInt(0))) {
-      sp := sp -% UInt(1)
+      sp := sp +% 1.U
+    } .elsewhen(io.pop && (sp > 0.U)) {
+      sp := sp -% 1.U
     }
-    when (sp > UInt(0)) {
-      out := stack_mem(sp -% UInt(1))
+    when (sp > 0.U) {
+      out := stack_mem(sp -% 1.U)
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 66a06435..ccfba499 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -14,10 +14,10 @@ class Tbl(w: Int, n: Int) extends Module {
     val wi  = Input(UInt.width(log2Up(n)))
     val ri  = Input(UInt.width(log2Up(n)))
     val we  = Input(Bool())
-    val  d  = Input(UInt.width(w))
-    val  o  = Output(UInt.width(w))
+    val  d  = Input(UInt(w.W))
+    val  o  = Output(UInt(w.W))
   })
-  val m = Mem(n, UInt.width(w))
+  val m = Mem(n, UInt(w.W))
   io.o := m(io.ri)
   when (io.we) {
     m(io.wi) := io.d
@@ -28,17 +28,17 @@ class Tbl(w: Int, n: Int) extends Module {
 }
 
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), idxs.size)
+  val (cnt, wrap) = Counter(true.B, idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt(_)))
-  val vidxs = Vec(idxs.map(UInt(_)))
-  val prev_idx = vidxs(cnt - UInt(1))
-  val prev_value = vvalues(cnt - UInt(1))
+  val vvalues = Vec(values.map(_.asUInt))
+  val vidxs = Vec(idxs.map(_.asUInt))
+  val prev_idx = vidxs(cnt - 1.U)
+  val prev_value = vvalues(cnt - 1.U)
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
-  dut.io.we := Bool(true) //TODO enSequence
+  dut.io.we := true.B //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt(0)) {
+  when (cnt > 0.U) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index b2e811d9..c0d64a43 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -25,13 +25,13 @@ class FinishTester extends BasicTester {
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt(test_wire_override_value))
+  assert(test_wire === test_wire_override_value.asUInt)
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt(test_wire_override_value)
+    test_wire := test_wire_override_value.asUInt
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index ad5aecd8..addd753f 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -8,15 +8,15 @@ import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt.width(16))
-    val b = Input(UInt.width(16))
-    val addout = Output(UInt.width(16))
-    val subout = Output(UInt.width(16))
-    val timesout = Output(UInt.width(16))
-    val divout = Output(UInt.width(16))
-    val modout = Output(UInt.width(16))
-    val lshiftout = Output(UInt.width(16))
-    val rshiftout = Output(UInt.width(16))
+    val a = Input(UInt(16.W))
+    val b = Input(UInt(16.W))
+    val addout = Output(UInt(16.W))
+    val subout = Output(UInt(16.W))
+    val timesout = Output(UInt(16.W))
+    val divout = Output(UInt(16.W))
+    val modout = Output(UInt(16.W))
+    val lshiftout = Output(UInt(16.W))
+    val rshiftout = Output(UInt(16.W))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt(0), UInt(1), b)
+  io.divout := a / Mux(b === 0.U, 1.U, b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt(0)
+  io.modout := 0.U
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
@@ -78,7 +78,7 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
 
 class GoodBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt.width(1))
+    val u = Input(UInt(1.W))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
@@ -86,7 +86,7 @@ class GoodBoolConversion extends Module {
 
 class BadBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt.width( 5))
+    val u = Input(UInt(5.W))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 0d5a2188..90e337a8 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -13,7 +13,7 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt(b))
+    assert(a === b.asUInt)
   }
   stop()
 }
@@ -31,12 +31,12 @@ class TabulateTester(n: Int) extends BasicTester {
 }
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), n*2)
+  val (cnt, wrap) = Counter(true.B, n*2)
   val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt(n)) {
-    val expected = cnt - UInt(n)
+  when (cnt >= n.asUInt) {
+    val expected = cnt - n.asUInt
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index b8e3a154..bcf59e03 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
   * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
   */
 class Packet extends Bundle {
-  val header = UInt.width(1)
+  val header = UInt(1.W)
 }
 
 /**
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 00b1e7de..c474430b 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -11,7 +11,7 @@ class VendingMachine extends Module {
     val dime   = Input(Bool())
     val valid  = Output(Bool())
   })
-  val c = UInt(5, width = 3)
+  val c = 5.U(3.W)
   val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
   val state = Reg(init = sIdle)
   when (state === sIdle) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 6dc2dbac..d4491e13 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -11,44 +11,44 @@ import chisel3.util._
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-  when(Bool(true)) { cnt.inc() }
-
-  val out = Wire(UInt.width(3))
-  when(cnt.value === UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value === UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value === UInt(2)) {
-    out := UInt(3)
+  when(true.B) { cnt.inc() }
+
+  val out = Wire(UInt(3.W))
+  when(cnt.value === 0.U) {
+    out := 1.U
+  } .elsewhen (cnt.value === 1.U) {
+    out := 2.U
+  } .elsewhen (cnt.value === 2.U) {
+    out := 3.U
   } .otherwise {
-    out := UInt(0)
+    out := 0.U
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + 1.U)
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === 3.U) {
     stop()
   }
 }
 
 class OverlappedWhenTester() extends BasicTester {
   val cnt = Counter(4)
-  when(Bool(true)) { cnt.inc() }
-
-  val out = Wire(UInt.width(3))
-  when(cnt.value <= UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value <= UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value <= UInt(2)) {
-    out := UInt(3)
+  when(true.B) { cnt.inc() }
+
+  val out = Wire(UInt(3.W))
+  when(cnt.value <= 0.U) {
+    out := 1.U
+  } .elsewhen (cnt.value <= 1.U) {
+    out := 2.U
+  } .elsewhen (cnt.value <= 2.U) {
+    out := 3.U
   } .otherwise {
-    out := UInt(0)
+    out := 0.U
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + 1.U)
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === 3.U) {
     stop()
   }
 }
diff --git a/src/test/scala/cookbook/Bundle2UInt.scala b/src/test/scala/cookbook/Bundle2UInt.scala
index d74218a8..cb9498d1 100644
--- a/src/test/scala/cookbook/Bundle2UInt.scala
+++ b/src/test/scala/cookbook/Bundle2UInt.scala
@@ -11,17 +11,17 @@ import chisel3._
 class Bundle2UInt extends CookbookTester(0) {
   // Example
   class MyBundle extends Bundle {
-    val foo = UInt(width = 4)
-    val bar = UInt(width = 4)
+    val foo = UInt(4.W)
+    val bar = UInt(4.W)
   }
   val bundle = Wire(new MyBundle)
-  bundle.foo := UInt(0xc)
-  bundle.bar := UInt(0x3)
+  bundle.foo := 0xc.U
+  bundle.bar := 0x3.U
   val uint = bundle.asUInt
   printf(p"$uint") // 195
 
   // Test
-  assert(uint === UInt(0xc3))
+  assert(uint === 0xc3.U)
 }
 
 class Bundle2UIntSpec  extends CookbookSpec {
diff --git a/src/test/scala/cookbook/CookbookSpec.scala b/src/test/scala/cookbook/CookbookSpec.scala
index b244f3cf..6ecea446 100644
--- a/src/test/scala/cookbook/CookbookSpec.scala
+++ b/src/test/scala/cookbook/CookbookSpec.scala
@@ -18,7 +18,7 @@ abstract class CookbookTester(length: Int) extends BasicTester {
   // No IO allowed, cookbook tests must be self-contained
   override final val io = new Bundle { }
 
-  val (cycle, done) = Counter(Bool(true), length)
+  val (cycle, done) = Counter(true.B, length)
   when (done) { stop() }
 }
 
diff --git a/src/test/scala/cookbook/UInt2Bundle.scala b/src/test/scala/cookbook/UInt2Bundle.scala
index fbf7fe8a..3ce4eebf 100644
--- a/src/test/scala/cookbook/UInt2Bundle.scala
+++ b/src/test/scala/cookbook/UInt2Bundle.scala
@@ -11,16 +11,16 @@ import chisel3._
 class UInt2Bundle extends CookbookTester(0) {
   // Example
   class MyBundle extends Bundle {
-    val foo = UInt(width = 4)
-    val bar = UInt(width = 4)
+    val foo = UInt(4.W)
+    val bar = UInt(4.W)
   }
-  val uint = UInt(0xb4)
+  val uint = 0xb4.U
   val bundle = (new MyBundle).fromBits(uint)
   printf(p"$bundle") // Bundle(foo -> 11, bar -> 4)
 
   // Test
-  assert(bundle.foo === UInt(0xb))
-  assert(bundle.bar === UInt(0x4))
+  assert(bundle.foo === 0xb.U)
+  assert(bundle.bar === 0x4.U)
 }
 
 class UInt2BundleSpec extends CookbookSpec {
diff --git a/src/test/scala/cookbook/UInt2VecOfBool.scala b/src/test/scala/cookbook/UInt2VecOfBool.scala
index ad4a0334..09d538f9 100644
--- a/src/test/scala/cookbook/UInt2VecOfBool.scala
+++ b/src/test/scala/cookbook/UInt2VecOfBool.scala
@@ -11,15 +11,15 @@ import chisel3._
  */
 class UInt2VecOfBool extends CookbookTester(0) {
   // Example
-  val uint = UInt(0xc)
+  val uint = 0xc.U
   val vec = Vec(uint.toBools)
   printf(p"$vec") // Vec(0, 0, 1, 1)
 
   // Test
-  assert(vec(0) === Bool(false))
-  assert(vec(1) === Bool(false))
-  assert(vec(2) === Bool(true))
-  assert(vec(3) === Bool(true))
+  assert(vec(0) === false.B)
+  assert(vec(1) === false.B)
+  assert(vec(2) === true.B)
+  assert(vec(3) === true.B)
 }
 
 class UInt2VecOfBoolSpec extends CookbookSpec {
diff --git a/src/test/scala/cookbook/VecOfBool2UInt.scala b/src/test/scala/cookbook/VecOfBool2UInt.scala
index 5852120c..531e4e68 100644
--- a/src/test/scala/cookbook/VecOfBool2UInt.scala
+++ b/src/test/scala/cookbook/VecOfBool2UInt.scala
@@ -10,7 +10,7 @@ import chisel3._
  */
 class VecOfBool2UInt extends CookbookTester(0) {
   // Example
-  val vec = Vec(Bool(true), Bool(false), Bool(true), Bool(true))
+  val vec = Vec(true.B, false.B, true.B, true.B)
   val uint = vec.asUInt
   printf(p"$uint") // 13
   
@@ -18,7 +18,7 @@ class VecOfBool2UInt extends CookbookTester(0) {
    *
    * (remember leftmost Bool in Vec is low order bit)
    */
-  assert(UInt(0xd) === uint)
+  assert(0xd.U === uint)
 }
 
 class VecOfBool2UIntSpec  extends CookbookSpec {
-- 
cgit v1.2.3


From 73906fcc796b259c81d5df7733968b77fbb81ba8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:06:57 -0800
Subject: All remaining automatable regex re-styles

---
 src/test/scala/chiselTests/BitwiseOps.scala    | 4 ++--
 src/test/scala/chiselTests/ComplexAssign.scala | 2 +-
 src/test/scala/chiselTests/MemorySearch.scala  | 2 +-
 src/test/scala/chiselTests/OptionBundle.scala  | 4 ++--
 src/test/scala/chiselTests/Risc.scala          | 2 +-
 src/test/scala/chiselTests/Vec.scala           | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 08999a1b..b8efaccf 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -9,8 +9,8 @@ import chisel3.testers.BasicTester
 
 class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
-  val a = UInt(_a, w)
-  val b = UInt(_b, w)
+  val a = _a.asUInt(w.W)
+  val b = _b.asUInt(w.W)
   assert(~a === UInt(mask & ~_a))
   assert((a & b) === UInt(_a & _b))
   assert((a | b) === UInt(_a | _b))
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index f7484501..a13ec959 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -36,7 +36,7 @@ class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends Basic
   val dut = Module(new ComplexAssign(32))
   dut.io.in.re := re.asUInt
   dut.io.in.im := im.asUInt
-  dut.io.e := Vec(enList.map(Bool(_)))(cnt)
+  dut.io.e := Vec(enList.map(_.asBool))(cnt)
   val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, 0.U)
   val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, 0.U)
   assert(re_correct && im_correct)
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index befbf010..4cbedf58 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -14,7 +14,7 @@ class MemorySearch extends Module {
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
   val index = Reg(init = 0.U(3.W))
-  val elts  = Vec(vals.map(UInt(_,4)))
+  val elts  = Vec(vals.map(_.asUInt(4.W)))
   // val elts  = Mem(UInt(32.W), 8) TODO ????
   val elt  = elts(index)
   val end  = !io.en && ((elt === io.target) || (index === 7.U))
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index d1b9152d..2ac661ea 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -26,8 +26,8 @@ class OptionBundleModule(hasIn: Boolean) extends Module {
 
 class SomeOptionBundleTester(expected: Boolean) extends BasicTester {
   val mod = Module(new OptionBundleModule(true))
-  mod.io.in.get := Bool(expected)
-  assert(mod.io.out === Bool(expected))
+  mod.io.in.get := expected.asBool
+  assert(mod.io.out === expected.asBool)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index ae99df59..744e3631 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -73,7 +73,7 @@ class RiscTester(c: Risc) extends Tester(c) {
     step(1)
   }
   def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
-    // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue()
+    // val cr = Cat(op, rc.asUInt(8.W), ra.asUInt(8.W), rb.asUInt(8.W)).litValue()
     val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
     println("I = " + cr)    // scalastyle:ignore regex
     cr
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 90e337a8..c621c1e1 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 //import chisel3.core.ExplicitCompileOptions.Strict
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
-  val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
+  val v = Vec(values.map(_.asUInt(w.W))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
     assert(a === b.asUInt)
   }
-- 
cgit v1.2.3


From 37a569372c70a651c813d0beb44124878a596e73 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:16:40 -0800
Subject: Fix all deprecations from new style

---
 src/test/scala/chiselTests/BitwiseOps.scala       | 8 ++++----
 src/test/scala/chiselTests/Counter.scala          | 6 +++---
 src/test/scala/chiselTests/MulLookup.scala        | 6 +++---
 src/test/scala/chiselTests/Stack.scala            | 2 +-
 src/test/scala/chiselTests/Tbl.scala              | 4 ++--
 src/test/scala/chiselTests/TesterDriverSpec.scala | 2 +-
 src/test/scala/chiselTests/Vec.scala              | 8 ++++----
 7 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index b8efaccf..1292222c 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = _a.asUInt(w.W)
   val b = _b.asUInt(w.W)
-  assert(~a === UInt(mask & ~_a))
-  assert((a & b) === UInt(_a & _b))
-  assert((a | b) === UInt(_a | _b))
-  assert((a ^ b) === UInt(_a ^ _b))
+  assert(~a === (mask & ~_a).asUInt)
+  assert((a & b) === (_a & _b).asUInt)
+  assert((a | b) === (_a | _b).asUInt)
+  assert((a ^ b) === (_a ^ _b).asUInt)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index cccd8c0e..55c07772 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(true.B) { cnt.inc() }
-  when(cnt.value === UInt(max-1)) {
+  when(cnt.value === (max-1).asUInt) {
     stop()
   }
 }
@@ -25,7 +25,7 @@ class EnableTester(seed: Int) extends BasicTester {
   val (_, done) = Counter(true.B, 33)
 
   when(done) {
-    assert(cntEnVal === UInt(popCount(seed)))
+    assert(cntEnVal === popCount(seed).asUInt)
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(true.B, max)
   when(wrap) {
-    assert(cnt === UInt(max - 1))
+    assert(cnt === (max - 1).asUInt)
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index f0b2aa21..936f3a45 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -11,13 +11,13 @@ class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
     val x   = Input(UInt(w.W))
     val y   = Input(UInt(w.W))
-    val z   = Output(UInt.width(2 * w))
+    val z   = Output(UInt((2 * w).W))
   })
   val tbl = Vec(
     for {
       i <- 0 until 1 << w
       j <- 0 until 1 << w
-    } yield UInt(i * j, 2 * w)
+    } yield (i * j).asUInt((2 * w).W)
   )
   io.z := tbl(((io.x << w) | io.y))
 }
@@ -26,7 +26,7 @@ class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
   dut.io.x := x.asUInt
   dut.io.y := y.asUInt
-  assert(dut.io.z === UInt(x * y))
+  assert(dut.io.z === (x * y).asUInt)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ce8fd9fc..58a05937 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module {
   })
 
   val stack_mem = Mem(depth, UInt(32.W))
-  val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
+  val sp        = Reg(init = 0.U(log2Up(depth+1).W))
   val out       = Reg(init = 0.U(32.W))
 
   when (io.en) {
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index ccfba499..03b08709 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -11,8 +11,8 @@ import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
-    val wi  = Input(UInt.width(log2Up(n)))
-    val ri  = Input(UInt.width(log2Up(n)))
+    val wi  = Input(UInt(log2Up(n).W))
+    val ri  = Input(UInt(log2Up(n).W))
     val we  = Input(Bool())
     val  d  = Input(UInt(w.W))
     val  o  = Output(UInt(w.W))
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index c0d64a43..e32368e9 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -21,7 +21,7 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = Wire(init=UInt(1, test_wire_width))
+  val test_wire = Wire(init=1.U(test_wire_width.W))
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index c621c1e1..4822d892 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -19,9 +19,9 @@ class ValueTester(w: Int, values: List[Int]) extends BasicTester {
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt(i*2))
+  val v = Vec(Range(0, n).map(i => (i*2).asUInt))
+  val x = Vec(Array.tabulate(n){ i => (i*2).asUInt })
+  val u = Vec.tabulate(n)(i => (i*2).asUInt)
 
   assert(v.asUInt() === x.asUInt())
   assert(v.asUInt() === u.asUInt())
@@ -32,7 +32,7 @@ class TabulateTester(n: Int) extends BasicTester {
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
   val (cnt, wrap) = Counter(true.B, n*2)
-  val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
+  val shifter = Reg(Vec(n, UInt(log2Up(n).W)))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
   when (cnt >= n.asUInt) {
-- 
cgit v1.2.3


From c270598ddb8cbfa32f8c86cc5187c89d00e6ded0 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:22:31 -0800
Subject: Remove () from as_Int

---
 src/test/scala/chiselTests/Risc.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 744e3631..57586c97 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -27,13 +27,13 @@ class Risc extends Module {
   val rai  = inst(15, 8)
   val rbi  = inst( 7, 0)
 
-  val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
-  val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
+  val ra = Mux(rai === 0.U, 0.U, file(rai))
+  val rb = Mux(rbi === 0.U, 0.U, file(rbi))
   val rc = Wire(Bits(32.W))
 
   io.valid := false.B
-  io.out   := 0.asUInt()
-  rc       := 0.asUInt()
+  io.out   := 0.U
+  rc       := 0.U
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
@@ -45,12 +45,12 @@ class Risc extends Module {
       is(imm_op) { rc := (rai << 8) | rbi }
     }
     io.out := rc
-    when (rci === 255.asUInt()) {
+    when (rci === 255.U) {
       io.valid := true.B
     } .otherwise {
       file(rci) := rc
     }
-    pc := pc +% 1.asUInt()
+    pc := pc +% 1.U
   }
 }
 
-- 
cgit v1.2.3


From 70161db5b6ae88b4ba1edfd8032e6ed381734dab Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 13:15:46 -0800
Subject: Convert rest of tests

---
 src/test/scala/chiselTests/BlackBox.scala | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 8b4cf157..7fcba766 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -89,25 +89,25 @@ class BlackBoxConstant(value: Int) extends BlackBox(
     Map("VALUE" -> value, "WIDTH" -> log2Up(value + 1))) {
   require(value >= 0, "value must be a UInt!")
   val io = IO(new Bundle {
-    val out = UInt(width = log2Up(value + 1)).asOutput
+    val out = UInt(log2Up(value + 1).W).asOutput
   })
 }
 
 class BlackBoxStringParam(str: String) extends BlackBox(Map("STRING" -> str)) {
   val io = IO(new Bundle {
-    val out = UInt(width = 32)
+    val out = UInt(32.W)
   })
 }
 
 class BlackBoxRealParam(dbl: Double) extends BlackBox(Map("REAL" -> dbl)) {
   val io = IO(new Bundle {
-    val out = UInt(width = 64)
+    val out = UInt(64.W)
   })
 }
 
 class BlackBoxTypeParam(w: Int, raw: String) extends BlackBox(Map("T" -> RawParam(raw))) {
   val io = IO(new Bundle {
-    val out = UInt(width = w)
+    val out = UInt(w.W)
   })
 }
 
@@ -127,7 +127,7 @@ class BlackBoxWithParamsTester extends BasicTester {
   assert(blackBoxFour.io.out === 4.U)
   assert(blackBoxStringParamOne.io.out === 1.U)
   assert(blackBoxStringParamTwo.io.out === 2.U)
-  assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U)
+  assert(blackBoxRealParamOne.io.out === BigInt(0x3ff0000000000000L).U)
   assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U)
   assert(blackBoxTypeParamBit.io.out === 1.U)
   assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W))
-- 
cgit v1.2.3


From 81e5d00d18a5ba9ae33c10219a270148002fc672 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 13:36:03 -0800
Subject: Deboilerplate the implicit conversions, add support for long.U

---
 src/test/scala/chiselTests/BlackBox.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 7fcba766..d42cd791 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -127,7 +127,7 @@ class BlackBoxWithParamsTester extends BasicTester {
   assert(blackBoxFour.io.out === 4.U)
   assert(blackBoxStringParamOne.io.out === 1.U)
   assert(blackBoxStringParamTwo.io.out === 2.U)
-  assert(blackBoxRealParamOne.io.out === BigInt(0x3ff0000000000000L).U)
+  assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U)
   assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U)
   assert(blackBoxTypeParamBit.io.out === 1.U)
   assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W))
-- 
cgit v1.2.3


From edb19a0559686a471141c74438f677c1e217a298 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 23 Nov 2016 16:01:50 -0800
Subject: Simplify Enum API (#385)

Get rid of some cruft exposed in #373

This also allows Bits.fromtInt(...) to be removed. Yay!

All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.

The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.---
 src/test/scala/chiselTests/Risc.scala           | 2 +-
 src/test/scala/chiselTests/VendingMachine.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 57586c97..0d03ff65 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -19,7 +19,7 @@ class Risc extends Module {
   val code = Mem(memSize, Bits(32.W))
   val pc   = Reg(init=0.U(8.W))
 
-  val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2)
+  val add_op :: imm_op :: Nil = Enum(2)
 
   val inst = code(pc)
   val op   = inst(31,24)
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index c474430b..712b5b7a 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -12,7 +12,7 @@ class VendingMachine extends Module {
     val valid  = Output(Bool())
   })
   val c = 5.U(3.W)
-  val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
+  val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(5)
   val state = Reg(init = sIdle)
   when (state === sIdle) {
     when (io.nickel) { state := s5 }
-- 
cgit v1.2.3