From d20591e0d030d5c380e279999659fbfa9f41d3d3 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 19 Nov 2015 16:03:53 -0800
Subject: Split internal and FIRRTL packages

---
 src/test/scala/chiselTests/ChiselSpec.scala | 2 +-
 src/test/scala/chiselTests/Reg.scala        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 8848d4f5..000880e2 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -11,7 +11,7 @@ import Chisel.testers._
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners {
   def execute(t: => BasicTester): Boolean = TesterDriver.execute(() => t)
-  def elaborate(t: => Module): Circuit = Driver.elaborate(() => t)
+  def elaborate(t: => Module): Unit = Driver.elaborate(() => t)
 }
 
 /** Spec base class for BDD-style testers. */
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 55c92b45..f2620d88 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -8,7 +8,7 @@ import Chisel.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
-    a [ChiselException] should be thrownBy {
+    a [Exception] should be thrownBy {
       val reg = Reg()
     }
   }
-- 
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