From 7dd2d7db355d8dd9e1fc49ed7cd479ce5273b691 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Fri, 30 Apr 2021 05:12:24 +0000
Subject: add helper function to convert chirrtl to firrtl. (#1854)

* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl.

* add scaladoc.

* add test.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/chiselTests/stage/ChiselStageSpec.scala | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
index 167e414b..7b6a2d39 100644
--- a/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
+++ b/src/test/scala/chiselTests/stage/ChiselStageSpec.scala
@@ -88,6 +88,13 @@ class ChiselStageSpec extends AnyFlatSpec with Matchers with Utils {
     catchWrites { ChiselStage.convert(new Foo) } shouldBe a[Right[_, _]]
   }
 
+  ignore should "generate a FIRRTL circuit from a CHIRRTL circuit" in {
+    info("no files were written")
+    catchWrites {
+      ChiselStage.convert(ChiselStage.elaborate(new Foo))
+    } shouldBe a[Right[_, _]]
+  }
+
   behavior of "ChiselStage$.emitChirrtl"
 
   ignore should "generate a CHIRRTL string from a Chisel module" in {
-- 
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