From 69e27b2fd9e02d4e3a024eec0cafce5b4b46c10a Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 14 Sep 2020 10:17:49 -0700
Subject: Documentation and minor plugin changes. (#1573)

* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package

* Revert reg naming behavior (omit underscore)

* Added documentation and a test

* Addressed reviewer feedback.---
 src/test/scala/chiselTests/naming/NamePluginSpec.scala | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/naming/NamePluginSpec.scala b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
index fc90264d..946b557a 100644
--- a/src/test/scala/chiselTests/naming/NamePluginSpec.scala
+++ b/src/test/scala/chiselTests/naming/NamePluginSpec.scala
@@ -203,5 +203,23 @@ class NamePluginSpec extends ChiselFlatSpec with Utils {
       y
     }
   }
+
+  "Nested val declarations" should "all be named" in {
+    class Test extends MultiIOModule {
+      {
+        val a = {
+          val b = {
+            val c = Wire(UInt(3.W))
+            Wire(UInt(3.W))
+          }
+          Wire(UInt(3.W))
+        }
+      }
+    }
+
+    aspectTest(() => new Test) {
+      top: Test => Select.wires(top).map(_.instanceName) should be (List("a_b_c", "a_b", "a"))
+    }
+  }
 }
 
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