From 017bd6b9c96974df2a3c4f35e069d60fec001f2e Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Sat, 5 Nov 2022 22:31:07 +0000
Subject: Support Analog in DataView (#2782) (#2828)

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/experimental/DataView.scala  | 12 +++++++++++-
 .../scala/chiselTests/experimental/FlatIOSpec.scala     | 17 ++++++++++++++++-
 2 files changed, 27 insertions(+), 2 deletions(-)

(limited to 'src/test/scala')

diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 3673778b..cefc893c 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.experimental.dataview._
 import chisel3.experimental.conversions._
 import chisel3.experimental.DataMirror.internal.chiselTypeClone
-import chisel3.experimental.HWTuple2
+import chisel3.experimental.{Analog, HWTuple2}
 import chisel3.stage.ChiselStage
 import chisel3.util.{Decoupled, DecoupledIO}
 
@@ -91,6 +91,16 @@ class DataViewSpec extends ChiselFlatSpec {
     chirrtl should include("bar <= in")
   }
 
+  it should "handle viewing Analogs as Analogs" in {
+    class MyModule extends Module {
+      val foo = IO(Analog(8.W))
+      val bar = IO(Analog(8.W))
+      foo <> bar.viewAs[Analog]
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include("attach (foo, bar)")
+  }
+
   it should "handle viewing Bundles as their same concrete type" in {
     class MyBundle extends Bundle {
       val foo = UInt(8.W)
diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
index dfce447f..ebb7cbdb 100644
--- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
+++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.experimental
 import chisel3._
 import chisel3.util.Valid
 import chisel3.stage.ChiselStage.emitChirrtl
-import chisel3.experimental.FlatIO
+import chisel3.experimental.{Analog, FlatIO}
 import chiselTests.ChiselFlatSpec
 
 class FlatIOSpec extends ChiselFlatSpec {
@@ -48,4 +48,19 @@ class FlatIOSpec extends ChiselFlatSpec {
     val chirrtl = emitChirrtl(new MyModule)
     chirrtl should include("out[addr] <= in[addr]")
   }
+
+  it should "support Analog members" in {
+    class MyBundle extends Bundle {
+      val foo = Output(UInt(8.W))
+      val bar = Analog(8.W)
+    }
+    class MyModule extends RawModule {
+      val in = IO(Flipped(new MyBundle))
+      val out = IO(new MyBundle)
+      out <> in
+    }
+    val chirrtl = emitChirrtl(new MyModule)
+    chirrtl should include("out.foo <= in.foo")
+    chirrtl should include("attach (out.bar, in.bar)")
+  }
 }
-- 
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