From a290d77ef3e88b200ab61cd41fcd1a1138321b66 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 8 Mar 2017 17:38:14 -0800
Subject: Deprecate old Reg with nulls constructor (#455)

---
 src/test/scala/cookbook/FSM.scala      | 2 +-
 src/test/scala/cookbook/RegOfVec.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/cookbook')

diff --git a/src/test/scala/cookbook/FSM.scala b/src/test/scala/cookbook/FSM.scala
index 45359c9e..9cc0ef2a 100644
--- a/src/test/scala/cookbook/FSM.scala
+++ b/src/test/scala/cookbook/FSM.scala
@@ -17,7 +17,7 @@ class DetectTwoOnes extends Module {
   })
 
   val sNone :: sOne1 :: sTwo1s :: Nil = Enum(3)
-  val state = Reg(init = sNone)
+  val state = RegInit(sNone)
 
   io.out := (state === sTwo1s)
 
diff --git a/src/test/scala/cookbook/RegOfVec.scala b/src/test/scala/cookbook/RegOfVec.scala
index 3e55acff..ba784871 100644
--- a/src/test/scala/cookbook/RegOfVec.scala
+++ b/src/test/scala/cookbook/RegOfVec.scala
@@ -19,7 +19,7 @@ class RegOfVec extends CookbookTester(2) {
   //   Note that Seq.fill constructs 4 32-bit UInt literals with the value 0
   //   Vec(...) then constructs a Wire of these literals
   //   The Reg is then initialized to the value of the Wire (which gives it the same type)
-  val initRegOfVec = Reg(init = Vec(Seq.fill(4)(0.asUInt(32.W))))
+  val initRegOfVec = RegInit(Vec(Seq.fill(4)(0.U(32.W))))
 
   // Simple test (cycle comes from superclass)
   when (cycle === 2.U) { assert(regOfVec(2) === 123.U) }
-- 
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