From dbf4d546767d6983aec24dedf994651417ae2e50 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 12 Aug 2020 12:10:44 -0400 Subject: Switch to HowToSerialize for Emission (#1405) * Fix emit{Firrtl,Verilog} for CustomFileEmission Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and Verilog (emitVerilog) to look for Circuit and Verilog annotations instead of DeletedAnnotations. This is needed after migrating to the CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete emitter annotations. Signed-off-by: Schuyler Eldridge * Use CustomFileEmission for ChiselCircuitAnnotation Removes the explicit chisel3.phases.Emitter and instead does emission with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then prevents the need for passing around DeletedAnnotations. As a consequence, I removed an unnecessary run of a second Converter in the Driver. Signed-off-by: Schuyler Eldridge * Fix tests for use of CustomFileEmission trait Signed-off-by: Schuyler Eldridge * Fixes for newer CustomFileEmission API Signed-off-by: Schuyler Eldridge --- src/test/scala/chiselTests/ChiselSpec.scala | 2 +- src/test/scala/chiselTests/MuxSpec.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests') diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index 9518fb5c..e50f26e8 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -78,7 +78,7 @@ trait ChiselRunners extends Assertions with BackendCompilationUtilities { .execute(Array("--target-dir", createTestDirectory(this.getClass.getSimpleName).toString), Seq(ChiselGeneratorAnnotation(() => t))) .collectFirst { - case DeletedAnnotation(_, EmittedVerilogCircuitAnnotation(a)) => a.value + case EmittedVerilogCircuitAnnotation(a) => a.value }.getOrElse(fail("No Verilog circuit was emitted by the FIRRTL compiler!")) } } diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala index a995ea76..71f4cd86 100644 --- a/src/test/scala/chiselTests/MuxSpec.scala +++ b/src/test/scala/chiselTests/MuxSpec.scala @@ -38,7 +38,7 @@ class MuxLookupWrapper(keyWidth: Int, default: Int, mapping: () => Seq[(UInt, UI class MuxLookupExhaustiveSpec extends ChiselPropSpec { val keyWidth = 2 val default = 9 // must be less than 10 to avoid hex/decimal mismatches - val firrtlLit = s"""UInt<4>("h$default")""" + val firrtlLit = s"""UInt<4>("h0$default")""" val stage = new ChiselStage // Assumes there are no literals with 'UInt<4>("h09")' in the output FIRRTL -- cgit v1.2.3