From 89ef4d78e8f44f31df6530a6a4dee20d0ad0399f Mon Sep 17 00:00:00 2001 From: Chick Markley Date: Mon, 13 May 2019 18:08:25 -0700 Subject: RawModule with no reset should be able to use withClock method. (#1065) * RawModule with no reset should be able to use withClock method. - refactor ClockAndReset - now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params - convenience methods clock and reset tries to deref the option - ClockAndReset.empty is factory method for (None, None) - In Builder - forcedClock does not check resetOpt now - forcedReset does not check clockOpt now - withClock no longer looks at resetOpt - withReset no longer looks at clockOpt - Module starts with empty ClockAndReset * RawModule with no reset should be able to use withClock method. Refactor again based on @ducky64 comments - refactor away ClockAndReset, now builder just has a - currentClock - currentReset - withClock, withRest, withClockAndReset just use these fields directly * RawModule with no reset should be able to use withClock method. - Fixed typo in withReset handler, now picks up new reset --- src/test/scala/chiselTests/Clock.scala | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'src/test/scala/chiselTests') diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index 78d60ed2..f508bb81 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -2,21 +2,34 @@ package chiselTests -import org.scalatest._ -import org.scalatest.prop._ - import chisel3._ +import chisel3.experimental.RawModule import chisel3.testers.BasicTester -import chisel3.util._ class ClockAsUIntTester extends BasicTester { assert(true.B.asClock.asUInt === 1.U) stop() } +class WithClockAndNoReset extends RawModule { + val clock1 = IO(Input(Clock())) + val clock2 = IO(Input(Clock())) + val in = IO(Input(Bool())) + val out = IO(Output(Bool())) + val a = withClock(clock2) { + RegNext(in) + } + out := a +} + class ClockSpec extends ChiselPropSpec { property("Bool.asClock.asUInt should pass a signal through unaltered") { assertTesterPasses { new ClockAsUIntTester } } + + property("Should be able to use withClock in a module with no reset") { + val circuit = Driver.emit { () => new WithClockAndNoReset } + circuit.contains("reg a : UInt<1>, clock2") should be (true) + } } -- cgit v1.2.3