From b169f6db95f9778cf8968cc1042b7f810f9d8123 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 15 Nov 2022 05:28:10 +0000 Subject: fullModulePorts + Opaque Types Fix and Test (#2845) (#2846) (cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589) Co-authored-by: Megan Wachs --- src/test/scala/chiselTests/RecordSpec.scala | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/test/scala/chiselTests') diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala index 3414ec8a..5a5bcf67 100644 --- a/src/test/scala/chiselTests/RecordSpec.scala +++ b/src/test/scala/chiselTests/RecordSpec.scala @@ -284,6 +284,26 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils { testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo")) } + they should "work correctly with DataMirror in nested OpaqueType Records" in { + var mod: NestedRecordModule = null + ChiselStage.elaborate { mod = new NestedRecordModule; mod } + val ports = chisel3.experimental.DataMirror.fullModulePorts(mod.inst) + val expectedPorts = Seq( + ("clock", mod.inst.clock), + ("reset", mod.inst.reset), + ("io", mod.inst.io), + ("io_bar", mod.inst.io.bar), + ("io_bar", mod.inst.io.bar.k), + ("io_bar", mod.inst.io.bar.k.k), + ("io_bar", mod.inst.io.bar.k.k.elements.head._2), + ("io_foo", mod.inst.io.foo), + ("io_foo", mod.inst.io.foo.k), + ("io_foo", mod.inst.io.foo.k.k), + ("io_foo", mod.inst.io.foo.k.k.elements.head._2) + ) + ports shouldBe expectedPorts + } + they should "work correctly when connecting nested OpaqueType elements" in { val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule } nestedRecordChirrtl should include("input in : UInt<8>") -- cgit v1.2.3 From 41d0d4cd075130cb6b4e41a7c7b6183830b5b9bc Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Wed, 7 Dec 2022 00:41:55 +0000 Subject: Make PriorityMux stack safe (backport #2854) (#2855) * Make PriorityMux stack safe (#2854) It used to be implemented with recursion, now it's implemented with a stack safe reverse and foldLeft. Also there were no tests for PriorityMux so I added one which helps prove the change is functionally correct. (cherry picked from commit 269ce472e9aa0c242fc028871a1fd5b045c82f83) # Conflicts: # src/test/scala/chiselTests/util/PipeSpec.scala * Resolve backport conflicts Co-authored-by: Jack Koenig Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>--- .../scala/chiselTests/util/PriorityMuxSpec.scala | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 src/test/scala/chiselTests/util/PriorityMuxSpec.scala (limited to 'src/test/scala/chiselTests') diff --git a/src/test/scala/chiselTests/util/PriorityMuxSpec.scala b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala new file mode 100644 index 00000000..32cf2431 --- /dev/null +++ b/src/test/scala/chiselTests/util/PriorityMuxSpec.scala @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chiselTests.util + +import chisel3._ +import chisel3.util.{is, switch, Counter, PriorityMux} +import chisel3.testers.BasicTester +import chisel3.stage.ChiselStage.emitChirrtl + +import chiselTests.ChiselFlatSpec + +class PriorityMuxTester extends BasicTester { + + val sel = Wire(UInt(3.W)) + sel := 0.U // default + + val elts = Seq(5.U, 6.U, 7.U) + val muxed = PriorityMux(sel, elts) + + // Priority is given to lowest order bit + val tests = Seq( + 1.U -> elts(0), + 2.U -> elts(1), + 3.U -> elts(0), + 4.U -> elts(2), + 5.U -> elts(0), + 6.U -> elts(1), + 7.U -> elts(0) + ) + val (cycle, done) = Counter(0 until tests.size + 1) + + for (((in, out), idx) <- tests.zipWithIndex) { + when(cycle === idx.U) { + sel := in + assert(muxed === out) + } + } + + when(done) { + stop() + } +} + +class PriorityMuxSpec extends ChiselFlatSpec { + behavior.of("PriorityMux") + + it should "be functionally correct" in { + assertTesterPasses(new PriorityMuxTester) + } + + it should "be stack safe" in { + emitChirrtl(new RawModule { + val n = 1 << 15 + val in = IO(Input(Vec(n, UInt(8.W)))) + val sel = IO(Input(UInt(n.W))) + val out = IO(Output(UInt(8.W))) + out := PriorityMux(sel, in) + }) + } +} -- cgit v1.2.3 From 044b062468c90a1084221e480463515c668e99df Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sat, 10 Dec 2022 10:45:37 +0000 Subject: Fix string interpolation in `util.exprimental.decode.bitset` (#2882) (#2883) * Fix BitSet decoder API when errorBit=False When errorBit is set to False, the original code will return `Unit` which will be `()` in interpolated string. * Add testcases for both errorBit cases in BitSetSpec (cherry picked from commit 42416cb6c6a3019fc29b9d98cfea3e3bb4e42684) Co-authored-by: Ocean Shen <30361859+OceanS2000@users.noreply.github.com>--- src/test/scala/chiselTests/util/BitSetSpec.scala | 29 +++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests') diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala index dd66ba40..cf5f54cf 100644 --- a/src/test/scala/chiselTests/util/BitSetSpec.scala +++ b/src/test/scala/chiselTests/util/BitSetSpec.scala @@ -110,9 +110,36 @@ class BitSetSpec extends AnyFlatSpec with Matchers { "b11??????" ) ), - true + errorBit = true ) }) } + it should "be decoded with DontCare error" in { + import chisel3._ + import chisel3.util.experimental.decode.decoder + // [0 - 256] part into: [0 - 31], [32 - 47, 64 - 127], [192 - 255] + // "0011????" "10??????" is empty to error + chisel3.stage.ChiselStage.emitSystemVerilog(new Module { + val in = IO(Input(UInt(8.W))) + val out = IO(Output(UInt(4.W))) + out := decoder.bitset( + in, + Seq( + BitSet.fromString( + "b000?????" + ), + BitSet.fromString( + """b0010???? + |b01?????? + |""".stripMargin + ), + BitSet.fromString( + "b11??????" + ) + ), + errorBit = false + ) + }) + } } -- cgit v1.2.3 From 116210ff806ccdda91b4c3343f78bad66783d0e6 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sat, 24 Dec 2022 17:45:37 +0000 Subject: FlatIOSpec: make sure the Analog test is using FLatIO (#2909) (#2910) (cherry picked from commit b91a2050aeb143aa80762dfb1b40f1e5035de4b5) Co-authored-by: Megan Wachs --- src/test/scala/chiselTests/experimental/FlatIOSpec.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests') diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala index ebb7cbdb..fb3f64c7 100644 --- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala +++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala @@ -55,9 +55,11 @@ class FlatIOSpec extends ChiselFlatSpec { val bar = Analog(8.W) } class MyModule extends RawModule { - val in = IO(Flipped(new MyBundle)) - val out = IO(new MyBundle) - out <> in + val io = FlatIO(new Bundle { + val in = Flipped(new MyBundle) + val out = new MyBundle + }) + io.out <> io.in } val chirrtl = emitChirrtl(new MyModule) chirrtl should include("out.foo <= in.foo") -- cgit v1.2.3