From 2979cb900c4f6773210dbe174091c08e13e6c52a Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 6 Oct 2016 09:21:03 -0700
Subject: Update Driver: Check the simulation exit code #281 Merge with master
 and support checking for failure with an explicit assertion message.

---
 src/test/scala/chiselTests/MultiAssign.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests')

diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fa4c4898..397ea4c2 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,7 +9,8 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
-  val cnt = Counter(2)
+  val countOnClockCycles = Bool(true)
+  val (cnt, wrap) = Counter(countOnClockCycles,2)
 
   val test = Wire(UInt.width(4))
   assert(test === 7.U)  // allow read references before assign references
@@ -20,7 +21,7 @@ class LastAssignTester() extends BasicTester {
   test := 7.U
   assert(test === 7.U)  // this obviously should work
 
-  when(cnt.value === 1.U) {
+  when(cnt === 1.U) {
     stop()
   }
 }
-- 
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