From e6c902eaf6f63413ff8f3b12ad8993cf34447413 Mon Sep 17 00:00:00 2001
From: Leway Colin
Date: Thu, 15 Jul 2021 07:22:20 +0800
Subject: Fix Cat rename signal (#2011)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/util/CatSpec.scala | 30 +++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
index 5565ca51..79d2c027 100644
--- a/src/test/scala/chiselTests/util/CatSpec.scala
+++ b/src/test/scala/chiselTests/util/CatSpec.scala
@@ -5,6 +5,7 @@ package chiselTests.util
 import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.util.Cat
+import chisel3.experimental.noPrefix
 
 import chiselTests.ChiselFlatSpec
 
@@ -31,4 +32,33 @@ class CatSpec extends ChiselFlatSpec {
 
   }
 
+  it should "not override the names of its arguments" in {
+    class MyModule extends RawModule {
+      val a, b, c, d = IO(Input(UInt(8.W)))
+      val out = IO(Output(UInt()))
+
+      out := Cat(a, b, c, d)
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    for (name <- Seq("a", "b", "c", "d")) {
+      chirrtl should include (s"input $name : UInt<8>")
+    }
+  }
+
+  it should "have prefixed naming" in {
+    class MyModule extends RawModule {
+      val in = IO(Input(Vec(8, UInt(8.W))))
+      val out = IO(Output(UInt()))
+
+      // noPrefix to avoid `out` as prefix
+      out := noPrefix(Cat(in))
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include ("node lo_lo = cat(in[6], in[7])")
+    chirrtl should include ("node lo_hi = cat(in[4], in[5])")
+    chirrtl should include ("node hi_lo = cat(in[2], in[3])")
+    chirrtl should include ("node hi_hi = cat(in[0], in[1])")
+  }
+
+
 }
-- 
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