From 2a56c6540e914611ac12647e157aec4c5c595758 Mon Sep 17 00:00:00 2001
From: Boyang Han
Date: Fri, 19 Mar 2021 01:28:56 +0800
Subject: Add toString method to BitPat (#1819)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/chiselTests/util/BitPatSpec.scala | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/BitPatSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala
new file mode 100644
index 00000000..a6c0acf7
--- /dev/null
+++ b/src/test/scala/chiselTests/util/BitPatSpec.scala
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util
+
+import chisel3.util.BitPat
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+
+class BitPatSpec extends AnyFlatSpec with Matchers {
+  behavior of classOf[BitPat].toString
+
+  it should "convert a BitPat to readable form" in {
+    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+    BitPat("b" + testPattern).toString should be (s"BitPat($testPattern)")
+  }
+}
-- 
cgit v1.2.3


From 1c1a4d7217574a938ad0ce529803fb991f9903f0 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Thu, 20 May 2021 06:50:10 +0000
Subject: Implement PLA (#1912)

* implement pla

* implement test for pla

* implement inverter matrix of PLA generator

* fix for review.

Co-authored-by: Boyang Han <yqszxx@gmail.com>---
 .../chiselTests/util/experimental/PlaSpec.scala    | 80 ++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/experimental/PlaSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
new file mode 100644
index 00000000..45ac012e
--- /dev/null
+++ b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
@@ -0,0 +1,80 @@
+package chiselTests.util.experimental
+
+import chisel3._
+import chisel3.stage.PrintFullStackTraceAnnotation
+import chisel3.testers.BasicTester
+import chisel3.util.{BitPat, pla}
+import chiselTests.ChiselFlatSpec
+
+class PlaSpec extends ChiselFlatSpec {
+  "A 1-of-8 decoder (eg. 74xx138 without enables)" should "be generated correctly" in {
+    assertTesterPasses(new BasicTester {
+      val table = Seq(
+        (BitPat("b000"), BitPat("b00000001")),
+        (BitPat("b001"), BitPat("b00000010")),
+        (BitPat("b010"), BitPat("b00000100")),
+        (BitPat("b011"), BitPat("b00001000")),
+        (BitPat("b100"), BitPat("b00010000")),
+        (BitPat("b101"), BitPat("b00100000")),
+        (BitPat("b110"), BitPat("b01000000")),
+        (BitPat("b111"), BitPat("b10000000")),
+      )
+      table.foreach { case (i, o) =>
+        val (plaIn, plaOut) = pla(table)
+        plaIn := WireDefault(i.value.U(3.W))
+        chisel3.assert(plaOut === o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+      }
+      stop()
+    })
+  }
+
+  "An active-low 1-of-8 decoder (eg. inverted 74xx138 without enables)" should "be generated correctly" in {
+    assertTesterPasses(new BasicTester {
+      val table = Seq(
+        (BitPat("b000"), BitPat("b00000001")),
+        (BitPat("b001"), BitPat("b00000010")),
+        (BitPat("b010"), BitPat("b00000100")),
+        (BitPat("b011"), BitPat("b00001000")),
+        (BitPat("b100"), BitPat("b00010000")),
+        (BitPat("b101"), BitPat("b00100000")),
+        (BitPat("b110"), BitPat("b01000000")),
+        (BitPat("b111"), BitPat("b10000000")),
+      )
+      table.foreach { case (i, o) =>
+        val (plaIn, plaOut) = pla(table, BitPat("b11111111"))
+        plaIn := WireDefault(i.value.U(3.W))
+        chisel3.assert(plaOut === ~o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+      }
+      stop()
+    })
+  }
+
+  "A simple PLA" should "be generated correctly" in {
+    assertTesterPasses(new BasicTester {
+      val table = Seq(
+        (BitPat("b0000"), BitPat("b1")),
+        (BitPat("b0001"), BitPat("b1")),
+        (BitPat("b0010"), BitPat("b0")),
+        (BitPat("b0011"), BitPat("b1")),
+        (BitPat("b0100"), BitPat("b1")),
+        (BitPat("b0101"), BitPat("b0")),
+        (BitPat("b0110"), BitPat("b0")),
+        (BitPat("b0111"), BitPat("b0")),
+        (BitPat("b1000"), BitPat("b0")),
+        (BitPat("b1001"), BitPat("b0")),
+        (BitPat("b1010"), BitPat("b1")),
+        (BitPat("b1011"), BitPat("b0")),
+        (BitPat("b1100"), BitPat("b0")),
+        (BitPat("b1101"), BitPat("b1")),
+        (BitPat("b1110"), BitPat("b1")),
+        (BitPat("b1111"), BitPat("b1")),
+      )
+      table.foreach { case (i, o) =>
+        val (plaIn, plaOut) = pla(table)
+        plaIn := WireDefault(i.value.U(4.W))
+        chisel3.assert(plaOut === o.value.U(1.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+      }
+      stop()
+    })
+  }
+}
-- 
cgit v1.2.3


From 6ccff4848fcf55cb1e865738a67f2bec25988ac8 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 26 May 2021 02:35:34 +0800
Subject: throw exception if BitPat width is 0  (#1920)

* spot a bug when BitPat width is 0

* fix #1919

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 src/test/scala/chiselTests/util/BitPatSpec.scala | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala
index a6c0acf7..ca8dd85c 100644
--- a/src/test/scala/chiselTests/util/BitPatSpec.scala
+++ b/src/test/scala/chiselTests/util/BitPatSpec.scala
@@ -14,4 +14,8 @@ class BitPatSpec extends AnyFlatSpec with Matchers {
     val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
     BitPat("b" + testPattern).toString should be (s"BitPat($testPattern)")
   }
+
+  it should "not fail if BitPat width is 0" in {
+    intercept[IllegalArgumentException]{BitPat("b")}
+  }
 }
-- 
cgit v1.2.3


From 71575609ae7242585ed1008b8473acae1a42165e Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Thu, 6 May 2021 16:18:58 +0000
Subject: implement TruthTable to represent a decode table.

---
 .../util/experimental/TruthTableSpec.scala         | 39 ++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
new file mode 100644
index 00000000..ed79f7f5
--- /dev/null
+++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util.experimental
+
+import chisel3.util.BitPat
+import chisel3.util.experimental.decode.TruthTable
+import org.scalatest.flatspec.AnyFlatSpec
+
+class TruthTableSpec extends AnyFlatSpec {
+  val table = TruthTable(
+    Map(
+      // BitPat("b000") -> BitPat("b0"),
+      BitPat("b001") -> BitPat("b?"),
+      BitPat("b010") -> BitPat("b?"),
+      // BitPat("b011") -> BitPat("b0"),
+      BitPat("b100") -> BitPat("b1"),
+      BitPat("b101") -> BitPat("b1"),
+      // BitPat("b110") -> BitPat("b0"),
+      BitPat("b111") -> BitPat("b1")
+    ),
+    BitPat("b0")
+  )
+  val str = """001->?
+              |010->?
+              |100->1
+              |101->1
+              |111->1
+              |0""".stripMargin
+  "TruthTable" should "serialize" in {
+    assert(table.toString contains "001->?")
+    assert(table.toString contains "010->?")
+    assert(table.toString contains "100->1")
+    assert(table.toString contains "111->1")
+    assert(table.toString contains "     0")
+  }
+  "TruthTable" should "deserialize" in {
+    assert(TruthTable(str) == table)
+  }
+}
-- 
cgit v1.2.3


From 28eef17430d8bbca2765b5a2b0ab0337f7484840 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Sun, 23 May 2021 07:55:48 +0000
Subject: TruthTable can merge same inputs now.

---
 .../util/experimental/TruthTableSpec.scala         | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
index ed79f7f5..743a3cd8 100644
--- a/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/TruthTableSpec.scala
@@ -36,4 +36,28 @@ class TruthTableSpec extends AnyFlatSpec {
   "TruthTable" should "deserialize" in {
     assert(TruthTable(str) == table)
   }
+  "TruthTable" should "merge same key" in {
+    assert(
+      TruthTable(
+        """001100->??1
+          |001100->1??
+          |???
+          |""".stripMargin
+      ) == TruthTable(
+        """001100->1?1
+          |???
+          |""".stripMargin
+      )
+    )
+  }
+  "TruthTable" should "crash when merging 0 and 1" in {
+    intercept[IllegalArgumentException] {
+      TruthTable(
+        """0->0
+          |0->1
+          |???
+          |""".stripMargin
+      )
+    }
+  }
 }
-- 
cgit v1.2.3


From b0c76525ed53c20dbbe4bd8eea4a9676d7247ec7 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Tue, 18 May 2021 14:53:59 +0000
Subject: test decode cache.

---
 .../util/experimental/DecoderSpec.scala            | 61 ++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/experimental/DecoderSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala b/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
new file mode 100644
index 00000000..3c9d490d
--- /dev/null
+++ b/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util.experimental
+
+import chisel3.util.experimental.decode.{DecodeTableAnnotation, Minimizer, QMCMinimizer, TruthTable}
+import chiselTests.SMTModelCheckingSpec
+import chiselTests.util.experimental.minimizer.DecodeTestModule
+import firrtl.annotations.ReferenceTarget
+
+class DecoderSpec extends SMTModelCheckingSpec {
+  val xor = TruthTable(
+    """10->1
+      |01->1
+      |    0""".stripMargin)
+
+  def minimizer: Minimizer = QMCMinimizer
+
+  "decoder" should "pass without DecodeTableAnnotation" in {
+    test(
+      () => new DecodeTestModule(minimizer, table = xor),
+      s"${minimizer.getClass.getSimpleName}.noAnno",
+      success
+    )
+  }
+
+  "decoder" should "fail with a incorrect DecodeTableAnnotation" in {
+    test(
+      () => new DecodeTestModule(minimizer, table = xor),
+      s"${minimizer.getClass.getSimpleName}.incorrectAnno",
+      fail(0),
+      annos = Seq(
+        DecodeTableAnnotation(ReferenceTarget("", "", Nil, "", Nil),
+          """10->1
+            |01->1
+            |    0""".stripMargin,
+          """10->1
+            |    0""".stripMargin
+        )
+      )
+    )
+  }
+
+  "decoder" should "success with a correct DecodeTableAnnotation" in {
+    test(
+      () => new DecodeTestModule(minimizer, table = xor),
+      s"${minimizer.getClass.getSimpleName}.correctAnno",
+      success,
+      annos = Seq(
+        DecodeTableAnnotation(ReferenceTarget("", "", Nil, "", Nil),
+          """10->1
+            |01->1
+            |    0""".stripMargin,
+          QMCMinimizer.minimize(TruthTable(
+            """10->1
+              |01->1
+              |    0""".stripMargin)).toString
+        )
+      )
+    )
+  }
+}
-- 
cgit v1.2.3


From 3a74d433560c8aca8bf9b2734a3ee620a3442117 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Thu, 6 May 2021 16:20:09 +0000
Subject: use z3 formal check minimized circuit and reference model.

---
 .../experimental/minimizer/MinimizerSpec.scala     | 104 +++++++++++++++++++++
 1 file changed, 104 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
new file mode 100644
index 00000000..9651f241
--- /dev/null
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util.experimental.minimizer
+
+import chisel3._
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.util._
+import chisel3.util.experimental.decode._
+import chisel3.util.pla
+import firrtl.backends.experimental.smt.EmittedSMTModelAnnotation
+import firrtl.options.TargetDirAnnotation
+import firrtl.util.BackendCompilationUtilities
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.matchers.should.Matchers
+
+class MinimizerSpec extends AnyFlatSpec with Matchers {
+  class DecodeTestModule(minimizer: Minimizer, table: TruthTable, reference: TruthTable) extends Module {
+    val i = IO(Input(UInt(table.table.head._1.getWidth.W)))
+    val (plaI, plaO) = pla(reference.table.toSeq, BitPat(reference.default.value.U))
+    plaI := i
+    chisel3.experimental.verification.assert((decoder(minimizer, i, table) === plaO) | (i === reference.default))
+  }
+
+  def test(minimizer: Minimizer, testcase: (TruthTable, TruthTable)) = {
+    val testDir = os.pwd / "test_run_dir" / "MinimizerSpec" / BackendCompilationUtilities.timeStamp
+    os.makeDir.all(testDir)
+    val checkFile = testDir / "check.smt"
+    os.write(checkFile,
+      (new ChiselStage).execute(
+        Array("-E", "experimental-smt2"),
+        Seq(
+          ChiselGeneratorAnnotation(() => new DecodeTestModule(minimizer, table = testcase._1, testcase._2)),
+          TargetDirAnnotation(testDir.toString)
+        )
+      ).collectFirst {
+        case EmittedSMTModelAnnotation(_, smt, _) => smt
+      }.get +
+        """; combinational logic check
+          |(declare-fun s0 () DecodeTestModule_s)
+          |(assert (not (DecodeTestModule_a s0)))
+          |(check-sat)
+          |""".stripMargin
+    )
+    os.proc("z3", checkFile).call().out.toString
+  }
+
+  val case0 = (
+    TruthTable(
+      Map(
+        BitPat("b000") -> BitPat("b0"),
+        // (BitPat("b001") -> BitPat("b?")),  // same as default, can be omitted
+        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
+        BitPat("b011") -> BitPat("b0"),
+        BitPat("b100") -> BitPat("b1"),
+        BitPat("b101") -> BitPat("b1"),
+        BitPat("b110") -> BitPat("b0"),
+        BitPat("b111") -> BitPat("b1")
+      ),
+      BitPat("b?")
+    ),
+    TruthTable(
+      Map(
+        BitPat("b000") -> BitPat("b0"),
+        // (BitPat("b001") -> BitPat("b?")),  // same as default, can be omitted
+        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
+        BitPat("b011") -> BitPat("b0"),
+        BitPat("b100") -> BitPat("b1"),
+        BitPat("b101") -> BitPat("b1"),
+        BitPat("b110") -> BitPat("b0"),
+        BitPat("b111") -> BitPat("b1")
+      ),
+      BitPat("b?")
+    )
+  )
+
+  val case1 = (
+    TruthTable(
+      Map(
+        BitPat("b000") -> BitPat("b0"),
+        BitPat("b001") -> BitPat("b0"),
+        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
+        (BitPat("b011") -> BitPat("b0")),
+        // (BitPat("b100") -> BitPat("b?")),  // same as default, can be omitted
+        // (BitPat("b101") -> BitPat("b?")),  // same as default, can be omitted
+        (BitPat("b110") -> BitPat("b1")),
+        (BitPat("b111") -> BitPat("b0"))
+      ),
+      BitPat("b?")
+    ),
+    TruthTable(
+      Map(
+        BitPat("b000") -> BitPat("b0"),
+        BitPat("b001") -> BitPat("b0"),
+        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
+        (BitPat("b011") -> BitPat("b0")),
+        // (BitPat("b100") -> BitPat("b?")),  // same as default, can be omitted
+        // (BitPat("b101") -> BitPat("b?")),  // same as default, can be omitted
+        (BitPat("b110") -> BitPat("b1")),
+        (BitPat("b111") -> BitPat("b0"))
+      ),
+      BitPat("b?")
+    ),
+  )
+}
-- 
cgit v1.2.3


From 38321a2eecfd7dc463ba640b2e97113043235b88 Mon Sep 17 00:00:00 2001
From: Boyang Han
Date: Tue, 11 May 2021 05:55:38 -0700
Subject: Add minimized form of test cases

---
 .../experimental/minimizer/MinimizerSpec.scala     | 34 +++++++---------------
 1 file changed, 11 insertions(+), 23 deletions(-)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
index 9651f241..0db6c0e2 100644
--- a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
@@ -48,8 +48,8 @@ class MinimizerSpec extends AnyFlatSpec with Matchers {
     TruthTable(
       Map(
         BitPat("b000") -> BitPat("b0"),
-        // (BitPat("b001") -> BitPat("b?")),  // same as default, can be omitted
-        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
+        // BitPat("b001") -> BitPat("b?"),  // same as default, can be omitted
+        // BitPat("b010") -> BitPat("b?"),  // same as default, can be omitted
         BitPat("b011") -> BitPat("b0"),
         BitPat("b100") -> BitPat("b1"),
         BitPat("b101") -> BitPat("b1"),
@@ -60,14 +60,8 @@ class MinimizerSpec extends AnyFlatSpec with Matchers {
     ),
     TruthTable(
       Map(
-        BitPat("b000") -> BitPat("b0"),
-        // (BitPat("b001") -> BitPat("b?")),  // same as default, can be omitted
-        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
-        BitPat("b011") -> BitPat("b0"),
-        BitPat("b100") -> BitPat("b1"),
-        BitPat("b101") -> BitPat("b1"),
-        BitPat("b110") -> BitPat("b0"),
-        BitPat("b111") -> BitPat("b1")
+        BitPat("b10?") -> BitPat("b1"),
+        BitPat("b1?1") -> BitPat("b1"),
       ),
       BitPat("b?")
     )
@@ -78,25 +72,19 @@ class MinimizerSpec extends AnyFlatSpec with Matchers {
       Map(
         BitPat("b000") -> BitPat("b0"),
         BitPat("b001") -> BitPat("b0"),
-        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
+        // BitPat("b010") -> BitPat("b?"),  // same as default, can be omitted
         (BitPat("b011") -> BitPat("b0")),
-        // (BitPat("b100") -> BitPat("b?")),  // same as default, can be omitted
-        // (BitPat("b101") -> BitPat("b?")),  // same as default, can be omitted
-        (BitPat("b110") -> BitPat("b1")),
-        (BitPat("b111") -> BitPat("b0"))
+        // BitPat("b100") -> BitPat("b?"),  // same as default, can be omitted
+        // BitPat("b101") -> BitPat("b?"),  // same as default, can be omitted
+        BitPat("b110") -> BitPat("b1"),
+        BitPat("b111") -> BitPat("b0")
       ),
       BitPat("b?")
     ),
     TruthTable(
       Map(
-        BitPat("b000") -> BitPat("b0"),
-        BitPat("b001") -> BitPat("b0"),
-        // (BitPat("b010") -> BitPat("b?")),  // same as default, can be omitted
-        (BitPat("b011") -> BitPat("b0")),
-        // (BitPat("b100") -> BitPat("b?")),  // same as default, can be omitted
-        // (BitPat("b101") -> BitPat("b?")),  // same as default, can be omitted
-        (BitPat("b110") -> BitPat("b1")),
-        (BitPat("b111") -> BitPat("b0"))
+        BitPat("b?10") -> BitPat("b1"),
+        // BitPat("b1?0") -> BitPat("b1"),  // both are ok
       ),
       BitPat("b?")
     ),
-- 
cgit v1.2.3


From ce755215d2657c81b4a2a161e0f04b1f6c59d5a1 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 12 May 2021 13:12:43 +0000
Subject: switch to EndToEndSMTBaseSpec

---
 .../experimental/minimizer/MinimizerSpec.scala     | 78 +++++++---------------
 1 file changed, 24 insertions(+), 54 deletions(-)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
index 0db6c0e2..6513dc64 100644
--- a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
@@ -3,49 +3,36 @@
 package chiselTests.util.experimental.minimizer
 
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import chisel3.util.experimental.decode._
 import chisel3.util.pla
-import firrtl.backends.experimental.smt.EmittedSMTModelAnnotation
-import firrtl.options.TargetDirAnnotation
-import firrtl.util.BackendCompilationUtilities
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.should.Matchers
+import chiselTests.SMTModelCheckingSpec
 
-class MinimizerSpec extends AnyFlatSpec with Matchers {
-  class DecodeTestModule(minimizer: Minimizer, table: TruthTable, reference: TruthTable) extends Module {
-    val i = IO(Input(UInt(table.table.head._1.getWidth.W)))
-    val (plaI, plaO) = pla(reference.table.toSeq, BitPat(reference.default.value.U))
-    plaI := i
-    chisel3.experimental.verification.assert((decoder(minimizer, i, table) === plaO) | (i === reference.default))
-  }
+class DecodeTestModule(minimizer: Minimizer, table: TruthTable) extends Module {
+  val i = IO(Input(UInt(table.table.head._1.getWidth.W)))
+  val (unminimizedI, unminimizedO) = pla(table.table.toSeq)
+  unminimizedI := i
+  val minimizedO: UInt = decoder(minimizer, i, table)
+
+  chisel3.experimental.verification.assert(
+    // for each instruction, if input matches, output should match, not no matched, fallback to default
+    (table.table.map { case (key, value) => (i === key) && (minimizedO === value) } ++
+      Seq(table.table.keys.map(i =/= _).reduce(_ && _) && minimizedO === table.default)).reduce(_ || _)
+  )
+}
 
-  def test(minimizer: Minimizer, testcase: (TruthTable, TruthTable)) = {
-    val testDir = os.pwd / "test_run_dir" / "MinimizerSpec" / BackendCompilationUtilities.timeStamp
-    os.makeDir.all(testDir)
-    val checkFile = testDir / "check.smt"
-    os.write(checkFile,
-      (new ChiselStage).execute(
-        Array("-E", "experimental-smt2"),
-        Seq(
-          ChiselGeneratorAnnotation(() => new DecodeTestModule(minimizer, table = testcase._1, testcase._2)),
-          TargetDirAnnotation(testDir.toString)
-        )
-      ).collectFirst {
-        case EmittedSMTModelAnnotation(_, smt, _) => smt
-      }.get +
-        """; combinational logic check
-          |(declare-fun s0 () DecodeTestModule_s)
-          |(assert (not (DecodeTestModule_a s0)))
-          |(check-sat)
-          |""".stripMargin
+trait MinimizerSpec extends SMTModelCheckingSpec {
+  def minimizer: Minimizer
+
+  def minimizerTest(testcase: TruthTable, caseName: String) = {
+    test(
+      () => new DecodeTestModule(minimizer, table = testcase),
+      s"${minimizer.getClass.getSimpleName}.$caseName",
+      success
     )
-    os.proc("z3", checkFile).call().out.toString
   }
 
-  val case0 = (
-    TruthTable(
+  val case0 = TruthTable(
       Map(
         BitPat("b000") -> BitPat("b0"),
         // BitPat("b001") -> BitPat("b?"),  // same as default, can be omitted
@@ -57,18 +44,9 @@ class MinimizerSpec extends AnyFlatSpec with Matchers {
         BitPat("b111") -> BitPat("b1")
       ),
       BitPat("b?")
-    ),
-    TruthTable(
-      Map(
-        BitPat("b10?") -> BitPat("b1"),
-        BitPat("b1?1") -> BitPat("b1"),
-      ),
-      BitPat("b?")
     )
-  )
 
-  val case1 = (
-    TruthTable(
+  val case1 = TruthTable(
       Map(
         BitPat("b000") -> BitPat("b0"),
         BitPat("b001") -> BitPat("b0"),
@@ -80,13 +58,5 @@ class MinimizerSpec extends AnyFlatSpec with Matchers {
         BitPat("b111") -> BitPat("b0")
       ),
       BitPat("b?")
-    ),
-    TruthTable(
-      Map(
-        BitPat("b?10") -> BitPat("b1"),
-        // BitPat("b1?0") -> BitPat("b1"),  // both are ok
-      ),
-      BitPat("b?")
-    ),
-  )
+    )
 }
-- 
cgit v1.2.3


From 37ec9eb3c3008939605bddfad9096d9b2b47ccdc Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Sat, 15 May 2021 15:45:26 +0000
Subject: Add test cases.

---
 .../experimental/minimizer/MinimizerSpec.scala     | 227 +++++++++++++++++++--
 1 file changed, 212 insertions(+), 15 deletions(-)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
index 6513dc64..a9e56800 100644
--- a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
@@ -32,11 +32,47 @@ trait MinimizerSpec extends SMTModelCheckingSpec {
     )
   }
 
-  val case0 = TruthTable(
+  // Term that being commented out is the result of which is same as default,
+  // making optimization opportunities to decoder algorithms
+
+  "case0" should "pass" in {
+    minimizerTest(TruthTable(
+      Map(
+        // BitPat("b000") -> BitPat("b0"),
+        BitPat("b001") -> BitPat("b?"),
+        BitPat("b010") -> BitPat("b?"),
+        // BitPat("b011") -> BitPat("b0"),
+        BitPat("b100") -> BitPat("b1"),
+        BitPat("b101") -> BitPat("b1"),
+        // BitPat("b110") -> BitPat("b0"),
+        BitPat("b111") -> BitPat("b1")
+      ),
+      BitPat("b0")
+    ), "case0")
+  }
+
+  "case1" should "pass" in {
+    minimizerTest(TruthTable(
       Map(
         BitPat("b000") -> BitPat("b0"),
-        // BitPat("b001") -> BitPat("b?"),  // same as default, can be omitted
-        // BitPat("b010") -> BitPat("b?"),  // same as default, can be omitted
+        BitPat("b001") -> BitPat("b?"),
+        BitPat("b010") -> BitPat("b?"),
+        BitPat("b011") -> BitPat("b0"),
+        // BitPat("b100") -> BitPat("b1"),
+        // BitPat("b101") -> BitPat("b1"),
+        BitPat("b110") -> BitPat("b0"),
+        // BitPat("b111") -> BitPat("b1")
+      ),
+      BitPat("b1")
+    ), "case1")
+  }
+
+  "caseX" should "pass" in {
+    minimizerTest(TruthTable(
+      Map(
+        BitPat("b000") -> BitPat("b0"),
+        // BitPat("b001") -> BitPat("b?"),
+        // BitPat("b010") -> BitPat("b?"),
         BitPat("b011") -> BitPat("b0"),
         BitPat("b100") -> BitPat("b1"),
         BitPat("b101") -> BitPat("b1"),
@@ -44,19 +80,180 @@ trait MinimizerSpec extends SMTModelCheckingSpec {
         BitPat("b111") -> BitPat("b1")
       ),
       BitPat("b?")
-    )
+    ), "caseX")
+  }
 
-  val case1 = TruthTable(
+  "caseMultiDefault" should "pass" in {
+    minimizerTest(TruthTable(
       Map(
-        BitPat("b000") -> BitPat("b0"),
-        BitPat("b001") -> BitPat("b0"),
-        // BitPat("b010") -> BitPat("b?"),  // same as default, can be omitted
-        (BitPat("b011") -> BitPat("b0")),
-        // BitPat("b100") -> BitPat("b?"),  // same as default, can be omitted
-        // BitPat("b101") -> BitPat("b?"),  // same as default, can be omitted
-        BitPat("b110") -> BitPat("b1"),
-        BitPat("b111") -> BitPat("b0")
+        BitPat("b000") -> BitPat("b0100"),
+        BitPat("b001") -> BitPat("b?111"),
+        BitPat("b010") -> BitPat("b?000"),
+        BitPat("b011") -> BitPat("b0101"),
+        BitPat("b111") -> BitPat("b1101")
       ),
-      BitPat("b?")
-    )
+      BitPat("b?100")
+    ), "caseMultiDefault")
+  }
+
+  // A simple RV32I decode table example
+  "caseRV32I" should "pass" in {
+    val BEQ = "?????????????????000?????1100011"
+    val BNE = "?????????????????001?????1100011"
+    val BLT = "?????????????????100?????1100011"
+    val BGE = "?????????????????101?????1100011"
+    val BLTU = "?????????????????110?????1100011"
+    val BGEU = "?????????????????111?????1100011"
+    val JALR = "?????????????????000?????1100111"
+    val JAL = "?????????????????????????1101111"
+    val LUI = "?????????????????????????0110111"
+    val AUIPC = "?????????????????????????0010111"
+    val ADDI = "?????????????????000?????0010011"
+    val SLTI = "?????????????????010?????0010011"
+    val SLTIU = "?????????????????011?????0010011"
+    val XORI = "?????????????????100?????0010011"
+    val ORI = "?????????????????110?????0010011"
+    val ANDI = "?????????????????111?????0010011"
+    val ADD = "0000000??????????000?????0110011"
+    val SUB = "0100000??????????000?????0110011"
+    val SLL = "0000000??????????001?????0110011"
+    val SLT = "0000000??????????010?????0110011"
+    val SLTU = "0000000??????????011?????0110011"
+    val XOR = "0000000??????????100?????0110011"
+    val SRL = "0000000??????????101?????0110011"
+    val SRA = "0100000??????????101?????0110011"
+    val OR = "0000000??????????110?????0110011"
+    val AND = "0000000??????????111?????0110011"
+    val LB = "?????????????????000?????0000011"
+    val LH = "?????????????????001?????0000011"
+    val LW = "?????????????????010?????0000011"
+    val LBU = "?????????????????100?????0000011"
+    val LHU = "?????????????????101?????0000011"
+    val SB = "?????????????????000?????0100011"
+    val SH = "?????????????????001?????0100011"
+    val SW = "?????????????????010?????0100011"
+    val FENCE = "?????????????????000?????0001111"
+    val MRET = "00110000001000000000000001110011"
+    val WFI = "00010000010100000000000001110011"
+    val CEASE = "00110000010100000000000001110011"
+    val CSRRW = "?????????????????001?????1110011"
+    val CSRRS = "?????????????????010?????1110011"
+    val CSRRC = "?????????????????011?????1110011"
+    val CSRRWI = "?????????????????101?????1110011"
+    val CSRRSI = "?????????????????110?????1110011"
+    val CSRRCI = "?????????????????111?????1110011"
+    val SCALL = "00000000000000000000000001110011"
+    val SBREAK = "00000000000100000000000001110011"
+    val SLLI_RV32 = "0000000??????????001?????0010011"
+    val SRLI_RV32 = "0000000??????????101?????0010011"
+    val SRAI_RV32 = "0100000??????????101?????0010011"
+
+    val A1_X = "??"
+    val A1_ZERO = "00"
+    val A1_RS1 = "01"
+    val A1_PC = "10"
+
+    val IMM_X = "???"
+    val IMM_S = "000"
+    val IMM_SB = "001"
+    val IMM_U = "010"
+    val IMM_UJ = "011"
+    val IMM_I = "100"
+    val IMM_Z = "101"
+
+    val A2_X = "??"
+    val A2_ZERO = "00"
+    val A2_SIZE = "01"
+    val A2_RS2 = "10"
+    val A2_IMM = "11"
+
+    val X = "?"
+    val N = "0"
+    val Y = "1"
+
+    val DW_X = X
+    val DW_XPR = Y
+
+    val M_X = "?????"
+    val M_XRD = "00000"
+    val M_XWR = "00001"
+
+    val CSR_X = "???"
+    val CSR_N = "000"
+    val CSR_I = "100"
+    val CSR_W = "101"
+    val CSR_S = "110"
+    val CSR_C = "111"
+
+    val FN_X = "????"
+    val FN_ADD = "0000"
+    val FN_SL = "0001"
+    val FN_SEQ = "0010"
+    val FN_SNE = "0011"
+    val FN_XOR = "0100"
+    val FN_SR = "0101"
+    val FN_OR = "0110"
+    val FN_AND = "0111"
+    val FN_SUB = "1010"
+    val FN_SRA = "1011"
+    val FN_SLT = "1100"
+    val FN_SGE = "1101"
+    val FN_SLTU = "1110"
+    val FN_SGEU = "1111"
+
+    minimizerTest(TruthTable(
+      Map(
+        BNE -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SNE, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        BEQ -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SEQ, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        BLT -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SLT, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        BLTU -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SLTU, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        BGE -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SGE, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        BGEU -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SGEU, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        JAL -> Seq(Y, N, N, N, Y, N, N, N, N, A2_SIZE, A1_PC, IMM_UJ, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        JALR -> Seq(Y, N, N, N, N, Y, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        AUIPC -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_PC, IMM_U, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        LB -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        LH -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        LW -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        LBU -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        LHU -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SB -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_IMM, A1_RS1, IMM_S, DW_XPR, FN_ADD, Y, M_XWR, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        SH -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_IMM, A1_RS1, IMM_S, DW_XPR, FN_ADD, Y, M_XWR, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        SW -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_IMM, A1_RS1, IMM_S, DW_XPR, FN_ADD, Y, M_XWR, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
+        LUI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_U, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        ADDI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SLTI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SLT, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SLTIU -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SLTU, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        ANDI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_AND, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        ORI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_OR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        XORI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_XOR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        ADD -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SUB -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SUB, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SLT -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SLT, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SLTU -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SLTU, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        AND -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_AND, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        OR -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_OR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        XOR -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_XOR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SLL -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SL, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SRL -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SRA -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SRA, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        FENCE -> Seq(Y, N, N, N, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_N, N, Y, N, N),
+        SCALL -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
+        SBREAK -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
+        MRET -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
+        WFI -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
+        CEASE -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
+        CSRRW -> Seq(Y, N, N, N, N, N, N, Y, N, A2_ZERO, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_W, N, N, N, N),
+        CSRRS -> Seq(Y, N, N, N, N, N, N, Y, N, A2_ZERO, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_S, N, N, N, N),
+        CSRRC -> Seq(Y, N, N, N, N, N, N, Y, N, A2_ZERO, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_C, N, N, N, N),
+        CSRRWI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_Z, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_W, N, N, N, N),
+        CSRRSI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_Z, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_S, N, N, N, N),
+        CSRRCI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_Z, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_C, N, N, N, N),
+        SLLI_RV32 -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SL, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SRLI_RV32 -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+        SRAI_RV32 -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SRA, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
+      ).map { case (k, v) => BitPat(s"b$k") -> BitPat(s"b${v.reduce(_ + _)}") },
+      BitPat(s"b${Seq(N, X, X, X, X, X, X, X, X, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, X, X, X, X, X, X, X, CSR_X, X, X, X, X).reduce(_ + _)}")
+    ), "rv32i")
+  }
 }
-- 
cgit v1.2.3


From b860a814c6e5a9333d6c94b6c5fbee6daad7ba5c Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Sat, 15 May 2021 15:46:08 +0000
Subject: implement test for qmc

---
 .../scala/chiselTests/util/experimental/minimizer/QMCSpec.scala  | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala
new file mode 100644
index 00000000..fc770202
--- /dev/null
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util.experimental.minimizer
+import chisel3.util.experimental.decode.Minimizer
+import chisel3.util.experimental.decode.QMCMinimizer
+
+class QMCSpec extends MinimizerSpec {
+  override def minimizer: Minimizer = QMCMinimizer
+}
-- 
cgit v1.2.3


From 1e40c7e2a2fd227c752e4e4dc29925004f790f7d Mon Sep 17 00:00:00 2001
From: Boyang Han
Date: Wed, 23 Jun 2021 17:37:27 +0800
Subject: Add 7 segment display decoder test case

---
 .../util/experimental/minimizer/MinimizerSpec.scala    | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
index a9e56800..5e3be9a6 100644
--- a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
@@ -96,6 +96,24 @@ trait MinimizerSpec extends SMTModelCheckingSpec {
     ), "caseMultiDefault")
   }
 
+  "case7SegDecoder" should "pass" in {
+    minimizerTest(TruthTable(
+      Map(
+        BitPat("b0000") -> BitPat("b111111001"),
+        BitPat("b0001") -> BitPat("b011000001"),
+        BitPat("b0010") -> BitPat("b110110101"),
+        BitPat("b0011") -> BitPat("b111100101"),
+        BitPat("b0100") -> BitPat("b011001101"),
+        BitPat("b0101") -> BitPat("b101101101"),
+        BitPat("b0110") -> BitPat("b101111101"),
+        BitPat("b0111") -> BitPat("b111000001"),
+        BitPat("b1000") -> BitPat("b111111101"),
+        BitPat("b1001") -> BitPat("b111101101"),
+      ),
+      BitPat("b???????10")
+    ), "case7SegDecoder")
+  }
+
   // A simple RV32I decode table example
   "caseRV32I" should "pass" in {
     val BEQ = "?????????????????000?????1100011"
-- 
cgit v1.2.3


From 695864f5716626a15a7798dae048d8301940a2db Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Thu, 15 Jul 2021 02:32:06 +0800
Subject: Espresso Decoder (#1964)

Co-authored-by: Haoran Yuan <sinofp@tuta.io>
Co-authored-by: Boyang Han <yqszxx@gmail.com>---
 .../chiselTests/util/experimental/minimizer/EspressoSpec.scala   | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala
new file mode 100644
index 00000000..f3270cae
--- /dev/null
+++ b/src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiselTests.util.experimental.minimizer
+import chisel3.util.experimental.decode.EspressoMinimizer
+import chisel3.util.experimental.decode.Minimizer
+
+class EspressoSpec extends MinimizerSpec {
+  override def minimizer: Minimizer = EspressoMinimizer
+}
-- 
cgit v1.2.3


From e6c902eaf6f63413ff8f3b12ad8993cf34447413 Mon Sep 17 00:00:00 2001
From: Leway Colin
Date: Thu, 15 Jul 2021 07:22:20 +0800
Subject: Fix Cat rename signal (#2011)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 src/test/scala/chiselTests/util/CatSpec.scala | 30 +++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/CatSpec.scala b/src/test/scala/chiselTests/util/CatSpec.scala
index 5565ca51..79d2c027 100644
--- a/src/test/scala/chiselTests/util/CatSpec.scala
+++ b/src/test/scala/chiselTests/util/CatSpec.scala
@@ -5,6 +5,7 @@ package chiselTests.util
 import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.util.Cat
+import chisel3.experimental.noPrefix
 
 import chiselTests.ChiselFlatSpec
 
@@ -31,4 +32,33 @@ class CatSpec extends ChiselFlatSpec {
 
   }
 
+  it should "not override the names of its arguments" in {
+    class MyModule extends RawModule {
+      val a, b, c, d = IO(Input(UInt(8.W)))
+      val out = IO(Output(UInt()))
+
+      out := Cat(a, b, c, d)
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    for (name <- Seq("a", "b", "c", "d")) {
+      chirrtl should include (s"input $name : UInt<8>")
+    }
+  }
+
+  it should "have prefixed naming" in {
+    class MyModule extends RawModule {
+      val in = IO(Input(Vec(8, UInt(8.W))))
+      val out = IO(Output(UInt()))
+
+      // noPrefix to avoid `out` as prefix
+      out := noPrefix(Cat(in))
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include ("node lo_lo = cat(in[6], in[7])")
+    chirrtl should include ("node lo_hi = cat(in[4], in[5])")
+    chirrtl should include ("node hi_lo = cat(in[2], in[3])")
+    chirrtl should include ("node hi_hi = cat(in[0], in[1])")
+  }
+
+
 }
-- 
cgit v1.2.3


From 3840fec3d918f23df07a18311136ac6a1bc365e1 Mon Sep 17 00:00:00 2001
From: Kevin Laeufer
Date: Wed, 25 Aug 2021 12:38:56 -0700
Subject: replace custom model checker with chiseltest formal verify command
 (#2075)

* replace custom model checker with chiseltest formal verify command

* integration-tests can make use of chiseltest

This is a compromise solution to avoid issues
with binary compatibility breaking changes in chisel3.

* ci: move integration tests into separate job

* run integration tests only for one scala version

* ci: install espresso for integration tests

* Update build.sbt

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>---
 .../util/experimental/DecoderSpec.scala            |  61 -----
 .../util/experimental/minimizer/EspressoSpec.scala |   9 -
 .../experimental/minimizer/MinimizerSpec.scala     | 277 ---------------------
 .../util/experimental/minimizer/QMCSpec.scala      |   9 -
 4 files changed, 356 deletions(-)
 delete mode 100644 src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
 delete mode 100644 src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala
 delete mode 100644 src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
 delete mode 100644 src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala b/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
deleted file mode 100644
index 3c9d490d..00000000
--- a/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.experimental
-
-import chisel3.util.experimental.decode.{DecodeTableAnnotation, Minimizer, QMCMinimizer, TruthTable}
-import chiselTests.SMTModelCheckingSpec
-import chiselTests.util.experimental.minimizer.DecodeTestModule
-import firrtl.annotations.ReferenceTarget
-
-class DecoderSpec extends SMTModelCheckingSpec {
-  val xor = TruthTable(
-    """10->1
-      |01->1
-      |    0""".stripMargin)
-
-  def minimizer: Minimizer = QMCMinimizer
-
-  "decoder" should "pass without DecodeTableAnnotation" in {
-    test(
-      () => new DecodeTestModule(minimizer, table = xor),
-      s"${minimizer.getClass.getSimpleName}.noAnno",
-      success
-    )
-  }
-
-  "decoder" should "fail with a incorrect DecodeTableAnnotation" in {
-    test(
-      () => new DecodeTestModule(minimizer, table = xor),
-      s"${minimizer.getClass.getSimpleName}.incorrectAnno",
-      fail(0),
-      annos = Seq(
-        DecodeTableAnnotation(ReferenceTarget("", "", Nil, "", Nil),
-          """10->1
-            |01->1
-            |    0""".stripMargin,
-          """10->1
-            |    0""".stripMargin
-        )
-      )
-    )
-  }
-
-  "decoder" should "success with a correct DecodeTableAnnotation" in {
-    test(
-      () => new DecodeTestModule(minimizer, table = xor),
-      s"${minimizer.getClass.getSimpleName}.correctAnno",
-      success,
-      annos = Seq(
-        DecodeTableAnnotation(ReferenceTarget("", "", Nil, "", Nil),
-          """10->1
-            |01->1
-            |    0""".stripMargin,
-          QMCMinimizer.minimize(TruthTable(
-            """10->1
-              |01->1
-              |    0""".stripMargin)).toString
-        )
-      )
-    )
-  }
-}
diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala
deleted file mode 100644
index f3270cae..00000000
--- a/src/test/scala/chiselTests/util/experimental/minimizer/EspressoSpec.scala
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.experimental.minimizer
-import chisel3.util.experimental.decode.EspressoMinimizer
-import chisel3.util.experimental.decode.Minimizer
-
-class EspressoSpec extends MinimizerSpec {
-  override def minimizer: Minimizer = EspressoMinimizer
-}
diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
deleted file mode 100644
index 5e3be9a6..00000000
--- a/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
+++ /dev/null
@@ -1,277 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.experimental.minimizer
-
-import chisel3._
-import chisel3.util._
-import chisel3.util.experimental.decode._
-import chisel3.util.pla
-import chiselTests.SMTModelCheckingSpec
-
-class DecodeTestModule(minimizer: Minimizer, table: TruthTable) extends Module {
-  val i = IO(Input(UInt(table.table.head._1.getWidth.W)))
-  val (unminimizedI, unminimizedO) = pla(table.table.toSeq)
-  unminimizedI := i
-  val minimizedO: UInt = decoder(minimizer, i, table)
-
-  chisel3.experimental.verification.assert(
-    // for each instruction, if input matches, output should match, not no matched, fallback to default
-    (table.table.map { case (key, value) => (i === key) && (minimizedO === value) } ++
-      Seq(table.table.keys.map(i =/= _).reduce(_ && _) && minimizedO === table.default)).reduce(_ || _)
-  )
-}
-
-trait MinimizerSpec extends SMTModelCheckingSpec {
-  def minimizer: Minimizer
-
-  def minimizerTest(testcase: TruthTable, caseName: String) = {
-    test(
-      () => new DecodeTestModule(minimizer, table = testcase),
-      s"${minimizer.getClass.getSimpleName}.$caseName",
-      success
-    )
-  }
-
-  // Term that being commented out is the result of which is same as default,
-  // making optimization opportunities to decoder algorithms
-
-  "case0" should "pass" in {
-    minimizerTest(TruthTable(
-      Map(
-        // BitPat("b000") -> BitPat("b0"),
-        BitPat("b001") -> BitPat("b?"),
-        BitPat("b010") -> BitPat("b?"),
-        // BitPat("b011") -> BitPat("b0"),
-        BitPat("b100") -> BitPat("b1"),
-        BitPat("b101") -> BitPat("b1"),
-        // BitPat("b110") -> BitPat("b0"),
-        BitPat("b111") -> BitPat("b1")
-      ),
-      BitPat("b0")
-    ), "case0")
-  }
-
-  "case1" should "pass" in {
-    minimizerTest(TruthTable(
-      Map(
-        BitPat("b000") -> BitPat("b0"),
-        BitPat("b001") -> BitPat("b?"),
-        BitPat("b010") -> BitPat("b?"),
-        BitPat("b011") -> BitPat("b0"),
-        // BitPat("b100") -> BitPat("b1"),
-        // BitPat("b101") -> BitPat("b1"),
-        BitPat("b110") -> BitPat("b0"),
-        // BitPat("b111") -> BitPat("b1")
-      ),
-      BitPat("b1")
-    ), "case1")
-  }
-
-  "caseX" should "pass" in {
-    minimizerTest(TruthTable(
-      Map(
-        BitPat("b000") -> BitPat("b0"),
-        // BitPat("b001") -> BitPat("b?"),
-        // BitPat("b010") -> BitPat("b?"),
-        BitPat("b011") -> BitPat("b0"),
-        BitPat("b100") -> BitPat("b1"),
-        BitPat("b101") -> BitPat("b1"),
-        BitPat("b110") -> BitPat("b0"),
-        BitPat("b111") -> BitPat("b1")
-      ),
-      BitPat("b?")
-    ), "caseX")
-  }
-
-  "caseMultiDefault" should "pass" in {
-    minimizerTest(TruthTable(
-      Map(
-        BitPat("b000") -> BitPat("b0100"),
-        BitPat("b001") -> BitPat("b?111"),
-        BitPat("b010") -> BitPat("b?000"),
-        BitPat("b011") -> BitPat("b0101"),
-        BitPat("b111") -> BitPat("b1101")
-      ),
-      BitPat("b?100")
-    ), "caseMultiDefault")
-  }
-
-  "case7SegDecoder" should "pass" in {
-    minimizerTest(TruthTable(
-      Map(
-        BitPat("b0000") -> BitPat("b111111001"),
-        BitPat("b0001") -> BitPat("b011000001"),
-        BitPat("b0010") -> BitPat("b110110101"),
-        BitPat("b0011") -> BitPat("b111100101"),
-        BitPat("b0100") -> BitPat("b011001101"),
-        BitPat("b0101") -> BitPat("b101101101"),
-        BitPat("b0110") -> BitPat("b101111101"),
-        BitPat("b0111") -> BitPat("b111000001"),
-        BitPat("b1000") -> BitPat("b111111101"),
-        BitPat("b1001") -> BitPat("b111101101"),
-      ),
-      BitPat("b???????10")
-    ), "case7SegDecoder")
-  }
-
-  // A simple RV32I decode table example
-  "caseRV32I" should "pass" in {
-    val BEQ = "?????????????????000?????1100011"
-    val BNE = "?????????????????001?????1100011"
-    val BLT = "?????????????????100?????1100011"
-    val BGE = "?????????????????101?????1100011"
-    val BLTU = "?????????????????110?????1100011"
-    val BGEU = "?????????????????111?????1100011"
-    val JALR = "?????????????????000?????1100111"
-    val JAL = "?????????????????????????1101111"
-    val LUI = "?????????????????????????0110111"
-    val AUIPC = "?????????????????????????0010111"
-    val ADDI = "?????????????????000?????0010011"
-    val SLTI = "?????????????????010?????0010011"
-    val SLTIU = "?????????????????011?????0010011"
-    val XORI = "?????????????????100?????0010011"
-    val ORI = "?????????????????110?????0010011"
-    val ANDI = "?????????????????111?????0010011"
-    val ADD = "0000000??????????000?????0110011"
-    val SUB = "0100000??????????000?????0110011"
-    val SLL = "0000000??????????001?????0110011"
-    val SLT = "0000000??????????010?????0110011"
-    val SLTU = "0000000??????????011?????0110011"
-    val XOR = "0000000??????????100?????0110011"
-    val SRL = "0000000??????????101?????0110011"
-    val SRA = "0100000??????????101?????0110011"
-    val OR = "0000000??????????110?????0110011"
-    val AND = "0000000??????????111?????0110011"
-    val LB = "?????????????????000?????0000011"
-    val LH = "?????????????????001?????0000011"
-    val LW = "?????????????????010?????0000011"
-    val LBU = "?????????????????100?????0000011"
-    val LHU = "?????????????????101?????0000011"
-    val SB = "?????????????????000?????0100011"
-    val SH = "?????????????????001?????0100011"
-    val SW = "?????????????????010?????0100011"
-    val FENCE = "?????????????????000?????0001111"
-    val MRET = "00110000001000000000000001110011"
-    val WFI = "00010000010100000000000001110011"
-    val CEASE = "00110000010100000000000001110011"
-    val CSRRW = "?????????????????001?????1110011"
-    val CSRRS = "?????????????????010?????1110011"
-    val CSRRC = "?????????????????011?????1110011"
-    val CSRRWI = "?????????????????101?????1110011"
-    val CSRRSI = "?????????????????110?????1110011"
-    val CSRRCI = "?????????????????111?????1110011"
-    val SCALL = "00000000000000000000000001110011"
-    val SBREAK = "00000000000100000000000001110011"
-    val SLLI_RV32 = "0000000??????????001?????0010011"
-    val SRLI_RV32 = "0000000??????????101?????0010011"
-    val SRAI_RV32 = "0100000??????????101?????0010011"
-
-    val A1_X = "??"
-    val A1_ZERO = "00"
-    val A1_RS1 = "01"
-    val A1_PC = "10"
-
-    val IMM_X = "???"
-    val IMM_S = "000"
-    val IMM_SB = "001"
-    val IMM_U = "010"
-    val IMM_UJ = "011"
-    val IMM_I = "100"
-    val IMM_Z = "101"
-
-    val A2_X = "??"
-    val A2_ZERO = "00"
-    val A2_SIZE = "01"
-    val A2_RS2 = "10"
-    val A2_IMM = "11"
-
-    val X = "?"
-    val N = "0"
-    val Y = "1"
-
-    val DW_X = X
-    val DW_XPR = Y
-
-    val M_X = "?????"
-    val M_XRD = "00000"
-    val M_XWR = "00001"
-
-    val CSR_X = "???"
-    val CSR_N = "000"
-    val CSR_I = "100"
-    val CSR_W = "101"
-    val CSR_S = "110"
-    val CSR_C = "111"
-
-    val FN_X = "????"
-    val FN_ADD = "0000"
-    val FN_SL = "0001"
-    val FN_SEQ = "0010"
-    val FN_SNE = "0011"
-    val FN_XOR = "0100"
-    val FN_SR = "0101"
-    val FN_OR = "0110"
-    val FN_AND = "0111"
-    val FN_SUB = "1010"
-    val FN_SRA = "1011"
-    val FN_SLT = "1100"
-    val FN_SGE = "1101"
-    val FN_SLTU = "1110"
-    val FN_SGEU = "1111"
-
-    minimizerTest(TruthTable(
-      Map(
-        BNE -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SNE, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        BEQ -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SEQ, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        BLT -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SLT, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        BLTU -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SLTU, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        BGE -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SGE, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        BGEU -> Seq(Y, N, N, Y, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_SB, DW_X, FN_SGEU, N, M_X, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        JAL -> Seq(Y, N, N, N, Y, N, N, N, N, A2_SIZE, A1_PC, IMM_UJ, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        JALR -> Seq(Y, N, N, N, N, Y, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        AUIPC -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_PC, IMM_U, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        LB -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        LH -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        LW -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        LBU -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        LHU -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, Y, M_XRD, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SB -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_IMM, A1_RS1, IMM_S, DW_XPR, FN_ADD, Y, M_XWR, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        SH -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_IMM, A1_RS1, IMM_S, DW_XPR, FN_ADD, Y, M_XWR, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        SW -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_IMM, A1_RS1, IMM_S, DW_XPR, FN_ADD, Y, M_XWR, N, N, N, N, N, N, N, CSR_N, N, N, N, N),
-        LUI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_U, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        ADDI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SLTI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SLT, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SLTIU -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SLTU, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        ANDI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_AND, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        ORI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_OR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        XORI -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_XOR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        ADD -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SUB -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SUB, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SLT -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SLT, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SLTU -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SLTU, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        AND -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_AND, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        OR -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_OR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        XOR -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_XOR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SLL -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SL, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SRL -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SRA -> Seq(Y, N, N, N, N, N, Y, Y, N, A2_RS2, A1_RS1, IMM_X, DW_XPR, FN_SRA, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        FENCE -> Seq(Y, N, N, N, N, N, N, N, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_N, N, Y, N, N),
-        SCALL -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
-        SBREAK -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
-        MRET -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
-        WFI -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
-        CEASE -> Seq(Y, N, N, N, N, N, N, X, N, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, N, N, N, N, N, N, N, CSR_I, N, N, N, N),
-        CSRRW -> Seq(Y, N, N, N, N, N, N, Y, N, A2_ZERO, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_W, N, N, N, N),
-        CSRRS -> Seq(Y, N, N, N, N, N, N, Y, N, A2_ZERO, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_S, N, N, N, N),
-        CSRRC -> Seq(Y, N, N, N, N, N, N, Y, N, A2_ZERO, A1_RS1, IMM_X, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_C, N, N, N, N),
-        CSRRWI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_Z, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_W, N, N, N, N),
-        CSRRSI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_Z, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_S, N, N, N, N),
-        CSRRCI -> Seq(Y, N, N, N, N, N, N, N, N, A2_IMM, A1_ZERO, IMM_Z, DW_XPR, FN_ADD, N, M_X, N, N, N, N, N, N, Y, CSR_C, N, N, N, N),
-        SLLI_RV32 -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SL, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SRLI_RV32 -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SR, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-        SRAI_RV32 -> Seq(Y, N, N, N, N, N, N, Y, N, A2_IMM, A1_RS1, IMM_I, DW_XPR, FN_SRA, N, M_X, N, N, N, N, N, N, Y, CSR_N, N, N, N, N),
-      ).map { case (k, v) => BitPat(s"b$k") -> BitPat(s"b${v.reduce(_ + _)}") },
-      BitPat(s"b${Seq(N, X, X, X, X, X, X, X, X, A2_X, A1_X, IMM_X, DW_X, FN_X, N, M_X, X, X, X, X, X, X, X, CSR_X, X, X, X, X).reduce(_ + _)}")
-    ), "rv32i")
-  }
-}
diff --git a/src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala b/src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala
deleted file mode 100644
index fc770202..00000000
--- a/src/test/scala/chiselTests/util/experimental/minimizer/QMCSpec.scala
+++ /dev/null
@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests.util.experimental.minimizer
-import chisel3.util.experimental.decode.Minimizer
-import chisel3.util.experimental.decode.QMCMinimizer
-
-class QMCSpec extends MinimizerSpec {
-  override def minimizer: Minimizer = QMCMinimizer
-}
-- 
cgit v1.2.3


From e74b978d5188d9cd28e3520912d858d228136e75 Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Fri, 27 Aug 2021 04:37:34 +0800
Subject: add new APIs to BitPat (#2076)

* add Y and N to BitPat.

* add ## for BitPat.

* add rawString API.

* use rawString in decoder

* add select and slice to BitPat.---
 src/test/scala/chiselTests/util/BitPatSpec.scala | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/BitPatSpec.scala b/src/test/scala/chiselTests/util/BitPatSpec.scala
index ca8dd85c..0c83493f 100644
--- a/src/test/scala/chiselTests/util/BitPatSpec.scala
+++ b/src/test/scala/chiselTests/util/BitPatSpec.scala
@@ -15,7 +15,30 @@ class BitPatSpec extends AnyFlatSpec with Matchers {
     BitPat("b" + testPattern).toString should be (s"BitPat($testPattern)")
   }
 
+  it should "convert a BitPat to raw form" in {
+    val testPattern = "0" * 32 + "1" * 32 + "?" * 32 + "?01" * 32
+    BitPat("b" + testPattern).rawString should be(testPattern)
+  }
+
   it should "not fail if BitPat width is 0" in {
     intercept[IllegalArgumentException]{BitPat("b")}
   }
+
+  it should "contact BitPat via ##" in {
+    (BitPat.Y(4) ## BitPat.dontCare(3) ## BitPat.N(2)).toString should be (s"BitPat(1111???00)")
+  }
+
+  it should "index and return new BitPat" in {
+    val b = BitPat("b1001???")
+    b(0) should be(BitPat.dontCare(1))
+    b(6) should be(BitPat.Y())
+    b(5) should be(BitPat.N())
+  }
+
+  it should "slice and return new BitPat" in {
+    val b = BitPat("b1001???")
+    b(2, 0) should be(BitPat("b???"))
+    b(4, 3) should be(BitPat("b01"))
+    b(6, 6) should be(BitPat("b1"))
+  }
 }
-- 
cgit v1.2.3


From 89679a3c7b42f34d3b9e93dfb6972bc36b6af297 Mon Sep 17 00:00:00 2001
From: Boyang Han
Date: Mon, 6 Sep 2021 07:35:46 -0700
Subject: Add a test case to demonstrate the bug found in #2112

---
 .../scala/chiselTests/util/experimental/PlaSpec.scala    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
index 45ac012e..ced4f9dd 100644
--- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
@@ -49,6 +49,22 @@ class PlaSpec extends ChiselFlatSpec {
     })
   }
 
+  "#2112" should "be generated correctly" in {
+    assertTesterPasses(new BasicTester {
+      val table = Seq(
+        (BitPat("b0"), BitPat("b?0")),
+        (BitPat("b1"), BitPat("b?1")),
+        (BitPat("b?"), BitPat("b1?")),
+      )
+      table.foreach { case (i, o) =>
+        val (plaIn, plaOut) = pla(table)
+        plaIn := WireDefault(i.value.U(3.W))
+        chisel3.assert(plaOut === o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+      }
+      stop()
+    })
+  }
+
   "A simple PLA" should "be generated correctly" in {
     assertTesterPasses(new BasicTester {
       val table = Seq(
-- 
cgit v1.2.3


From 0ca4ce23400d3624f8f617aa8ae21880d8430c2e Mon Sep 17 00:00:00 2001
From: Boyang Han
Date: Mon, 6 Sep 2021 21:27:51 -0700
Subject: Test case rework

---
 src/test/scala/chiselTests/util/experimental/PlaSpec.scala | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'src/test/scala/chiselTests/util')

diff --git a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
index ced4f9dd..8af5c936 100644
--- a/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
+++ b/src/test/scala/chiselTests/util/experimental/PlaSpec.scala
@@ -52,14 +52,13 @@ class PlaSpec extends ChiselFlatSpec {
   "#2112" should "be generated correctly" in {
     assertTesterPasses(new BasicTester {
       val table = Seq(
-        (BitPat("b0"), BitPat("b?0")),
-        (BitPat("b1"), BitPat("b?1")),
-        (BitPat("b?"), BitPat("b1?")),
+        (BitPat("b000"), BitPat("b?01")),
+        (BitPat("b111"), BitPat("b?01")),
       )
       table.foreach { case (i, o) =>
         val (plaIn, plaOut) = pla(table)
         plaIn := WireDefault(i.value.U(3.W))
-        chisel3.assert(plaOut === o.value.U(8.W), "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
+        chisel3.assert(o === plaOut, "Input " + i.toString + " produced incorrect output BitPat(%b)", plaOut)
       }
       stop()
     })
-- 
cgit v1.2.3