From 0745dedefea901df029e65aa59846d8b561dfd31 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 22 Oct 2020 18:40:54 -0700 Subject: Use Data refs for name prefixing with aggregate elements (#1616) * Use Data refs for name prefixing with aggregate elements Vecs set the refs of their elements upon construction of those elements. In the past, Records haven't set their elements refs until module close, but it can be done sooner. Doing it upon binding means that refs will at least be available for Records used in hardware elements. Since only bound Data can be connected to anyway, Aggregate elements being connected to will always have a ref which we can then use for creating naming prefixes. * Add tighter correctness checks * Handle more cases in connection prefixing Add support for forcing setRef to override a previous setting. This is only used by BlackBox ports which need to drop their io prefix. Also add a Try() around Data.bindingToString which sometimes throws exceptions when being used to .toString a Data in an error message. * Strip trailing spaces in names in compiler plugin--- src/test/scala/chiselTests/naming/PrefixSpec.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/naming') diff --git a/src/test/scala/chiselTests/naming/PrefixSpec.scala b/src/test/scala/chiselTests/naming/PrefixSpec.scala index 27a9fd39..83408dea 100644 --- a/src/test/scala/chiselTests/naming/PrefixSpec.scala +++ b/src/test/scala/chiselTests/naming/PrefixSpec.scala @@ -285,6 +285,7 @@ class PrefixSpec extends ChiselPropSpec with Utils { wire.y := RegNext(3.U) wire.vec(0) := RegNext(3.U) wire.vec(wire.x) := RegNext(3.U) + wire.vec(1.U) := RegNext(3.U) } } aspectTest(() => new Test) { @@ -293,7 +294,8 @@ class PrefixSpec extends ChiselPropSpec with Utils { "wire_x_REG", "wire_y_REG", "wire_vec_0_REG", - "wire_vec_REG" + "wire_vec_REG", + "wire_vec_1_REG" )) } } -- cgit v1.2.3