From 3131c0daad41dea78bede4517669e376c41a325a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 10 Jan 2022 10:39:52 -0800
Subject: Apply scalafmt

Command:
sbt scalafmtAll
---
 .../scala/chiselTests/experimental/Tuple.scala     | 28 +++++++++++-----------
 1 file changed, 14 insertions(+), 14 deletions(-)

(limited to 'src/test/scala/chiselTests/experimental/Tuple.scala')

diff --git a/src/test/scala/chiselTests/experimental/Tuple.scala b/src/test/scala/chiselTests/experimental/Tuple.scala
index 5f897fbc..b57766e7 100644
--- a/src/test/scala/chiselTests/experimental/Tuple.scala
+++ b/src/test/scala/chiselTests/experimental/Tuple.scala
@@ -9,7 +9,7 @@ import chisel3.stage.ChiselStage
 
 class TupleSpec extends ChiselFlatSpec {
 
-  behavior of "Tuple"
+  behavior.of("Tuple")
 
   it should "enable using Tuple2 like Data" in {
     class MyModule extends Module {
@@ -20,8 +20,8 @@ class TupleSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign y = sel ? a : c;")
-    verilog should include ("assign z = sel ? b : d;")
+    verilog should include("assign y = sel ? a : c;")
+    verilog should include("assign z = sel ? b : d;")
   }
 
   it should "support nesting of tuples" in {
@@ -31,10 +31,10 @@ class TupleSpec extends ChiselFlatSpec {
       ((w, x), (y, z)) := ((a, b), (c, d))
     }
     val chirrtl = ChiselStage.emitChirrtl(new MyModule)
-    chirrtl should include ("w <= a")
-    chirrtl should include ("x <= b")
-    chirrtl should include ("y <= c")
-    chirrtl should include ("z <= d")
+    chirrtl should include("w <= a")
+    chirrtl should include("x <= b")
+    chirrtl should include("y <= c")
+    chirrtl should include("z <= d")
   }
 
   it should "enable using Tuple3 like Data" in {
@@ -47,9 +47,9 @@ class TupleSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign v = sel ? a : f;")
-    verilog should include ("assign w = sel ? b : g;")
-    verilog should include ("assign x = sel ? c : h;")
+    verilog should include("assign v = sel ? a : f;")
+    verilog should include("assign w = sel ? b : g;")
+    verilog should include("assign x = sel ? c : h;")
   }
 
   it should "enable using Tuple4 like Data" in {
@@ -62,10 +62,10 @@ class TupleSpec extends ChiselFlatSpec {
     }
     // Verilog instead of CHIRRTL because the optimizations make it much prettier
     val verilog = ChiselStage.emitVerilog(new MyModule)
-    verilog should include ("assign v = sel ? a : f;")
-    verilog should include ("assign w = sel ? b : g;")
-    verilog should include ("assign x = sel ? c : h;")
-    verilog should include ("assign y = sel ? d : i;")
+    verilog should include("assign v = sel ? a : f;")
+    verilog should include("assign w = sel ? b : g;")
+    verilog should include("assign x = sel ? c : h;")
+    verilog should include("assign y = sel ? d : i;")
   }
 
   it should "enable using Tuple5 like Data" in {
-- 
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