From 116210ff806ccdda91b4c3343f78bad66783d0e6 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sat, 24 Dec 2022 17:45:37 +0000 Subject: FlatIOSpec: make sure the Analog test is using FLatIO (#2909) (#2910) (cherry picked from commit b91a2050aeb143aa80762dfb1b40f1e5035de4b5) Co-authored-by: Megan Wachs --- src/test/scala/chiselTests/experimental/FlatIOSpec.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests/experimental/FlatIOSpec.scala') diff --git a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala index ebb7cbdb..fb3f64c7 100644 --- a/src/test/scala/chiselTests/experimental/FlatIOSpec.scala +++ b/src/test/scala/chiselTests/experimental/FlatIOSpec.scala @@ -55,9 +55,11 @@ class FlatIOSpec extends ChiselFlatSpec { val bar = Analog(8.W) } class MyModule extends RawModule { - val in = IO(Flipped(new MyBundle)) - val out = IO(new MyBundle) - out <> in + val io = FlatIO(new Bundle { + val in = Flipped(new MyBundle) + val out = new MyBundle + }) + io.out <> io.in } val chirrtl = emitChirrtl(new MyModule) chirrtl should include("out.foo <= in.foo") -- cgit v1.2.3