From 898142ba05b04fb1602b249fd1ae81baa3f47f89 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 12 Apr 2022 00:09:55 +0000
Subject: Enhance views to [sometimes] support dynamic indexing and implement
 FlatIO (backport #2476) (#2479)

* Capture 1:1 mappings of Aggregates inside of views

This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).

This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.

(cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e)

* Add FlatIO API for creating ports from Bundles without a prefix

(cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb)

* [docs] Add FlatIO to the general cookbook

(cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 .../scala/chiselTests/experimental/DataView.scala  | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'src/test/scala/chiselTests/experimental/DataView.scala')

diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala
index 0285a524..e7caacfd 100644
--- a/src/test/scala/chiselTests/experimental/DataView.scala
+++ b/src/test/scala/chiselTests/experimental/DataView.scala
@@ -332,6 +332,36 @@ class DataViewSpec extends ChiselFlatSpec {
     chirrtl should include("dataOut <= vec[addr]")
   }
 
+  it should "support dynamic indexing for Vecs that correspond 1:1 in a view" in {
+    class MyBundle extends Bundle {
+      val foo = Vec(4, UInt(8.W))
+      val bar = UInt(2.W)
+    }
+    implicit val myView = DataView[(Vec[UInt], UInt), MyBundle](
+      _ => new MyBundle,
+      _._1 -> _.foo,
+      _._2 -> _.bar
+    )
+    class MyModule extends Module {
+      val dataIn = IO(Input(UInt(8.W)))
+      val addr = IO(Input(UInt(2.W)))
+      val dataOut = IO(Output(UInt(8.W)))
+
+      val vec = RegInit(0.U.asTypeOf(Vec(4, UInt(8.W))))
+      val addrReg = Reg(UInt(2.W))
+      val view = (vec, addrReg).viewAs[MyBundle]
+      // Dynamic indexing is more of a "generator" in Chisel3 than an individual node
+      // This style is not recommended, this is just testing the behavior
+      val selected = view.foo(view.bar)
+      view.bar := addr
+      selected := dataIn
+      dataOut := selected
+    }
+    val chirrtl = ChiselStage.emitChirrtl(new MyModule)
+    chirrtl should include("vec[addrReg] <= dataIn")
+    chirrtl should include("dataOut <= vec[addrReg]")
+  }
+
   it should "error if you try to dynamically index a Vec view that does not correspond to a Vec target" in {
     class MyModule extends Module {
       val inA, inB = IO(Input(UInt(8.W)))
-- 
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