From 741761cfbac8d8b7e297666c66d91cb773a6f109 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Thu, 10 Mar 2022 01:10:30 +0000 Subject: Emit FIRRTL bulkconnects whenever possible (#2381) (#2440) Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung Co-authored-by: Jack Koenig (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig --- src/test/scala/chiselTests/experimental/DataView.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/test/scala/chiselTests/experimental/DataView.scala') diff --git a/src/test/scala/chiselTests/experimental/DataView.scala b/src/test/scala/chiselTests/experimental/DataView.scala index 5ef062fa..0285a524 100644 --- a/src/test/scala/chiselTests/experimental/DataView.scala +++ b/src/test/scala/chiselTests/experimental/DataView.scala @@ -103,8 +103,8 @@ class DataViewSpec extends ChiselFlatSpec { buzz.viewAs[MyBundle] := in } val chirrtl = ChiselStage.emitChirrtl(new MyModule) - chirrtl should include("fizz.foo <= in.foo") - chirrtl should include("buzz.foo <= in.foo") + chirrtl should include("fizz <= in") + chirrtl should include("buzz <= in") } it should "handle viewing Vecs as their same concrete type" in { @@ -116,8 +116,8 @@ class DataViewSpec extends ChiselFlatSpec { buzz.viewAs[Vec[UInt]] := in } val chirrtl = ChiselStage.emitChirrtl(new MyModule) - chirrtl should include("fizz[0] <= in[0]") - chirrtl should include("buzz[0] <= in[0]") + chirrtl should include("fizz <= in") + chirrtl should include("buzz <= in") } it should "handle viewing Vecs as Bundles and vice versa" in { -- cgit v1.2.3