From d997acb05e5a307afb7c9ad4c136b9b4e1506efc Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sun, 23 Oct 2022 19:01:43 +0000 Subject: Don't invalidate ExtModule ports in an explicitInvalidate = true context (backport #2795) (#2799) * Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795) * Don't invalidate ExtModule ports in an explicitInvalidate = true context ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`. (cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d) # Conflicts: # core/src/main/scala/chisel3/BlackBox.scala * Resolve backport conflicts Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig --- src/test/scala/chiselTests/aop/InjectionSpec.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/test/scala/chiselTests/aop') diff --git a/src/test/scala/chiselTests/aop/InjectionSpec.scala b/src/test/scala/chiselTests/aop/InjectionSpec.scala index 9b29b0ba..1b69efa3 100644 --- a/src/test/scala/chiselTests/aop/InjectionSpec.scala +++ b/src/test/scala/chiselTests/aop/InjectionSpec.scala @@ -108,6 +108,7 @@ class InjectionSpec extends ChiselFlatSpec with Utils { { _: SubmoduleManipulationTester => // By creating a second SubmoduleA, the module names would conflict unless they were uniquified val moduleSubmoduleC = Module(new SubmoduleC) + moduleSubmoduleC.io <> DontCare //if we're here then we've elaborated correctly stop() } -- cgit v1.2.3