From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 src/test/scala/chiselTests/VectorPacketIO.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/VectorPacketIO.scala')

diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index b8e3a154..bcf59e03 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
   * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
   */
 class Packet extends Bundle {
-  val header = UInt.width(1)
+  val header = UInt(1.W)
 }
 
 /**
-- 
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