From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 21 Jun 2016 09:17:30 -0700 Subject: New Module, IO, Input/Output wrapping. --- src/test/scala/chiselTests/Vec.scala | 30 ------------------------------ 1 file changed, 30 deletions(-) (limited to 'src/test/scala/chiselTests/Vec.scala') diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 943d9e4b..5239c6ba 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -41,32 +41,6 @@ class ShiftRegisterTester(n: Int) extends BasicTester { } } -class FunBundle extends Bundle { - val stuff = UInt(width = 10) -} - -class ZeroModule extends Module { - val io = new Bundle { - val mem = UInt(width = 10) - val interrupts = Vec(2, Bool()).asInput - val mmio_axi = Vec(0, new FunBundle) - val mmio_ahb = Vec(0, new FunBundle).flip - } - - io.mmio_axi <> io.mmio_ahb - - io.mem := UInt(0) - when (io.interrupts(0)) { io.mem := UInt(1) } - when (io.interrupts(1)) { io.mem := UInt(2) } -} - -class ZeroTester extends BasicTester { - val foo = Module(new ZeroModule) - foo.io.interrupts := Vec.tabulate(2) { _ => Bool(true) } - assert (foo.io.mem === UInt(2)) - stop() -} - class VecSpec extends ChiselPropSpec { property("Vecs should be assignable") { forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) => @@ -81,8 +55,4 @@ class VecSpec extends ChiselPropSpec { property("Regs of vecs should be usable as shift registers") { forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } } } - - property("Dual empty Vectors") { - assertTesterPasses{ new ZeroTester } - } } -- cgit v1.2.3 From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/test/scala/chiselTests/Vec.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests/Vec.scala') diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 943d9e4b..7dd80a13 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -2,10 +2,12 @@ package chiselTests -import Chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/test/scala/chiselTests/Vec.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests/Vec.scala') diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index b90c1f09..cdb1ba8d 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -12,7 +12,7 @@ import chisel3.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? for ((a,b) <- v.zip(values)) { - assert(a === UInt(b)) + assert(a === UInt.Lit(b)) } stop() } @@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester { val shifter = Reg(Vec(n, UInt(width = log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt - when (cnt >= UInt(n)) { - val expected = cnt - UInt(n) + when (cnt >= UInt.Lit(n)) { + val expected = cnt - UInt.Lit(n) assert(shifter(0) === expected) } when (wrap) { -- cgit v1.2.3 From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 17:08:55 -0700 Subject: More literal/width rangling. --- src/test/scala/chiselTests/Vec.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/test/scala/chiselTests/Vec.scala') diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index cdb1ba8d..22b518a2 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -18,9 +18,9 @@ class ValueTester(w: Int, values: List[Int]) extends BasicTester { } class TabulateTester(n: Int) extends BasicTester { - val v = Vec(Range(0, n).map(i => UInt(i * 2))) - val x = Vec(Array.tabulate(n){ i => UInt(i * 2) }) - val u = Vec.tabulate(n)(i => UInt(i*2)) + val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2))) + val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) }) + val u = Vec.tabulate(n)(i => UInt.Lit(i*2)) assert(v.toBits === x.toBits) assert(v.toBits === u.toBits) @@ -31,7 +31,7 @@ class TabulateTester(n: Int) extends BasicTester { class ShiftRegisterTester(n: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), n*2) - val shifter = Reg(Vec(n, UInt(width = log2Up(n)))) + val shifter = Reg(Vec(n, UInt.width(log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt when (cnt >= UInt.Lit(n)) { -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/test/scala/chiselTests/Vec.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/test/scala/chiselTests/Vec.scala') diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 22b518a2..e8bd66bd 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -12,15 +12,15 @@ import chisel3.util._ class ValueTester(w: Int, values: List[Int]) extends BasicTester { val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? for ((a,b) <- v.zip(values)) { - assert(a === UInt.Lit(b)) + assert(a === UInt(b)) } stop() } class TabulateTester(n: Int) extends BasicTester { - val v = Vec(Range(0, n).map(i => UInt.Lit(i * 2))) - val x = Vec(Array.tabulate(n){ i => UInt.Lit(i * 2) }) - val u = Vec.tabulate(n)(i => UInt.Lit(i*2)) + val v = Vec(Range(0, n).map(i => UInt(i * 2))) + val x = Vec(Array.tabulate(n){ i => UInt(i * 2) }) + val u = Vec.tabulate(n)(i => UInt(i*2)) assert(v.toBits === x.toBits) assert(v.toBits === u.toBits) @@ -34,8 +34,8 @@ class ShiftRegisterTester(n: Int) extends BasicTester { val shifter = Reg(Vec(n, UInt.width(log2Up(n)))) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt - when (cnt >= UInt.Lit(n)) { - val expected = cnt - UInt.Lit(n) + when (cnt >= UInt(n)) { + val expected = cnt - UInt(n) assert(shifter(0) === expected) } when (wrap) { -- cgit v1.2.3