From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001 From: ducky Date: Thu, 17 Nov 2016 13:01:03 -0800 Subject: Restyle a lot of test code, mainly with regex --- src/test/scala/chiselTests/TesterDriverSpec.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests/TesterDriverSpec.scala') diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index b2e811d9..c0d64a43 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -25,13 +25,13 @@ class FinishTester extends BasicTester { // though we just set test_wire to 1, the assert below will pass because // the finish will change its value - assert(test_wire === UInt(test_wire_override_value)) + assert(test_wire === test_wire_override_value.asUInt) /** In finish we use last connect semantics to alter the test_wire in the circuit * with a new value */ override def finish(): Unit = { - test_wire := UInt(test_wire_override_value) + test_wire := test_wire_override_value.asUInt } } -- cgit v1.2.3 From 37a569372c70a651c813d0beb44124878a596e73 Mon Sep 17 00:00:00 2001 From: ducky Date: Thu, 17 Nov 2016 13:16:40 -0800 Subject: Fix all deprecations from new style --- src/test/scala/chiselTests/TesterDriverSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/TesterDriverSpec.scala') diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala index c0d64a43..e32368e9 100644 --- a/src/test/scala/chiselTests/TesterDriverSpec.scala +++ b/src/test/scala/chiselTests/TesterDriverSpec.scala @@ -21,7 +21,7 @@ class FinishTester extends BasicTester { stop() } - val test_wire = Wire(init=UInt(1, test_wire_width)) + val test_wire = Wire(init=1.U(test_wire_width.W)) // though we just set test_wire to 1, the assert below will pass because // the finish will change its value -- cgit v1.2.3