From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 21 Jun 2016 09:17:30 -0700 Subject: New Module, IO, Input/Output wrapping. --- src/test/scala/chiselTests/Tbl.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index c79eb8a4..751dc127 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -8,13 +8,13 @@ import org.scalatest.prop._ import Chisel.testers.BasicTester class Tbl(w: Int, n: Int) extends Module { - val io = new Bundle { - val wi = UInt(INPUT, log2Up(n)) - val ri = UInt(INPUT, log2Up(n)) - val we = Bool(INPUT) - val d = UInt(INPUT, w) - val o = UInt(OUTPUT, w) - } + val io = IO(new Bundle { + val wi = Input(UInt(log2Up(n))) + val ri = Input(UInt(log2Up(n))) + val we = Input(Bool()) + val d = Input(UInt(w)) + val o = Output(UInt(w)) + }) val m = Mem(n, UInt(width = w)) io.o := m(io.ri) when (io.we) { -- cgit v1.2.3 From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/test/scala/chiselTests/Tbl.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index c79eb8a4..d84cd85e 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -2,10 +2,12 @@ package chiselTests -import Chisel._ import org.scalatest._ import org.scalatest.prop._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester +import chisel3.util._ class Tbl(w: Int, n: Int) extends Module { val io = new Bundle { -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/test/scala/chiselTests/Tbl.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 6ebe0875..75c4278f 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -14,8 +14,8 @@ class Tbl(w: Int, n: Int) extends Module { val wi = Input(UInt(log2Up(n))) val ri = Input(UInt(log2Up(n))) val we = Input(Bool()) - val d = Input(UInt(w)) - val o = Output(UInt(w)) + val d = Input(UInt.width(w)) + val o = Output(UInt.width(w)) }) val m = Mem(n, UInt(width = w)) io.o := m(io.ri) @@ -32,13 +32,13 @@ class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends Basi val dut = Module(new Tbl(w, n)) val vvalues = Vec(values.map(UInt(_))) val vidxs = Vec(idxs.map(UInt(_))) - val prev_idx = vidxs(cnt - UInt(1)) - val prev_value = vvalues(cnt - UInt(1)) + val prev_idx = vidxs(cnt - UInt.Lit(1)) + val prev_value = vvalues(cnt - UInt.Lit(1)) dut.io.wi := vidxs(cnt) dut.io.ri := prev_idx dut.io.we := Bool(true) //TODO enSequence dut.io.d := vvalues(cnt) - when (cnt > UInt(0)) { + when (cnt > UInt.Lit(0)) { when (prev_idx === vidxs(cnt)) { assert(dut.io.o === vvalues(cnt)) } .otherwise { -- cgit v1.2.3 From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 17:08:55 -0700 Subject: More literal/width rangling. --- src/test/scala/chiselTests/Tbl.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 75c4278f..40730264 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -11,13 +11,13 @@ import chisel3.util._ class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { - val wi = Input(UInt(log2Up(n))) - val ri = Input(UInt(log2Up(n))) + val wi = Input(UInt.width(log2Up(n))) + val ri = Input(UInt.width(log2Up(n))) val we = Input(Bool()) val d = Input(UInt.width(w)) val o = Output(UInt.width(w)) }) - val m = Mem(n, UInt(width = w)) + val m = Mem(n, UInt.width(w)) io.o := m(io.ri) when (io.we) { m(io.wi) := io.d @@ -30,8 +30,8 @@ class Tbl(w: Int, n: Int) extends Module { class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), idxs.size) val dut = Module(new Tbl(w, n)) - val vvalues = Vec(values.map(UInt(_))) - val vidxs = Vec(idxs.map(UInt(_))) + val vvalues = Vec(values.map(UInt.Lit(_))) + val vidxs = Vec(idxs.map(UInt.Lit(_))) val prev_idx = vidxs(cnt - UInt.Lit(1)) val prev_value = vvalues(cnt - UInt.Lit(1)) dut.io.wi := vidxs(cnt) -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/test/scala/chiselTests/Tbl.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 40730264..66a06435 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -30,15 +30,15 @@ class Tbl(w: Int, n: Int) extends Module { class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), idxs.size) val dut = Module(new Tbl(w, n)) - val vvalues = Vec(values.map(UInt.Lit(_))) - val vidxs = Vec(idxs.map(UInt.Lit(_))) - val prev_idx = vidxs(cnt - UInt.Lit(1)) - val prev_value = vvalues(cnt - UInt.Lit(1)) + val vvalues = Vec(values.map(UInt(_))) + val vidxs = Vec(idxs.map(UInt(_))) + val prev_idx = vidxs(cnt - UInt(1)) + val prev_value = vvalues(cnt - UInt(1)) dut.io.wi := vidxs(cnt) dut.io.ri := prev_idx dut.io.we := Bool(true) //TODO enSequence dut.io.d := vvalues(cnt) - when (cnt > UInt.Lit(0)) { + when (cnt > UInt(0)) { when (prev_idx === vidxs(cnt)) { assert(dut.io.o === vvalues(cnt)) } .otherwise { -- cgit v1.2.3 From 6df3a785f8abe706838bc5b4b35c3374b6512f96 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 12:17:48 -0700 Subject: Pass compileOptions as an implicit Module parameter. --- src/test/scala/chiselTests/Tbl.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 66a06435..2aa8b031 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -8,6 +8,7 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ +import chisel3.NotStrict.NotStrictCompileOptions class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { -- cgit v1.2.3 From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 13:45:05 -0700 Subject: Rename CompileOptions implicit objects. --- src/test/scala/chiselTests/Tbl.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 2aa8b031..df8ce02c 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -8,7 +8,7 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -import chisel3.NotStrict.NotStrictCompileOptions +import chisel3.NotStrict.CompileOptions class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { -- cgit v1.2.3 From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 11:44:09 -0700 Subject: Massive rename of CompileOptions. Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used. --- src/test/scala/chiselTests/Tbl.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index df8ce02c..5ff1aa31 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -8,7 +8,7 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -import chisel3.NotStrict.CompileOptions +//import chisel3.ExplicitCompileOptions.NotStrict class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { -- cgit v1.2.3 From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 14:57:42 -0700 Subject: Consolidate CompileOptions and re-enable NotStrict pending macro work. --- src/test/scala/chiselTests/Tbl.scala | 1 - 1 file changed, 1 deletion(-) (limited to 'src/test/scala/chiselTests/Tbl.scala') diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala index 5ff1aa31..66a06435 100644 --- a/src/test/scala/chiselTests/Tbl.scala +++ b/src/test/scala/chiselTests/Tbl.scala @@ -8,7 +8,6 @@ import org.scalatest.prop._ import chisel3._ import chisel3.testers.BasicTester import chisel3.util._ -//import chisel3.ExplicitCompileOptions.NotStrict class Tbl(w: Int, n: Int) extends Module { val io = IO(new Bundle { -- cgit v1.2.3