From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 21 Jun 2016 09:17:30 -0700
Subject: New Module, IO, Input/Output wrapping.

---
 src/test/scala/chiselTests/Tbl.scala | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'src/test/scala/chiselTests/Tbl.scala')

diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index c79eb8a4..751dc127 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -8,13 +8,13 @@ import org.scalatest.prop._
 import Chisel.testers.BasicTester
 
 class Tbl(w: Int, n: Int) extends Module {
-  val io = new Bundle {
-    val wi  = UInt(INPUT, log2Up(n))
-    val ri  = UInt(INPUT, log2Up(n))
-    val we  = Bool(INPUT)
-    val  d  = UInt(INPUT, w)
-    val  o  = UInt(OUTPUT, w)
-  }
+  val io = IO(new Bundle {
+    val wi  = Input(UInt(log2Up(n)))
+    val ri  = Input(UInt(log2Up(n)))
+    val we  = Input(Bool())
+    val  d  = Input(UInt(w))
+    val  o  = Output(UInt(w))
+  })
   val m = Mem(n, UInt(width = w))
   io.o := m(io.ri)
   when (io.we) {
-- 
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