From 083610b2faa456dfccc4365dd115565d36e522fa Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 21 Jun 2016 10:13:51 -0700 Subject: Most of the remaining tests with Module, IO wrapping. --- src/test/scala/chiselTests/Stack.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'src/test/scala/chiselTests/Stack.scala') diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index ac799c8a..46e5dc23 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -5,13 +5,13 @@ import scala.collection.mutable.Stack import Chisel._ class ChiselStack(val depth: Int) extends Module { - val io = new Bundle { - val push = Bool(INPUT) - val pop = Bool(INPUT) - val en = Bool(INPUT) - val dataIn = UInt(INPUT, 32) - val dataOut = UInt(OUTPUT, 32) - } + val io = IO(new Bundle { + val push = Input(Bool()) + val pop = Input(Bool()) + val en = Input(Bool()) + val dataIn = Input(UInt(32)) + val dataOut = Output(UInt(32)) + }) val stack_mem = Mem(depth, UInt(width = 32)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) -- cgit v1.2.3 From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/test/scala/chiselTests/Stack.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Stack.scala') diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index ac799c8a..cbd9f3e3 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -1,8 +1,11 @@ // See LICENSE for license details. package chiselTests + import scala.collection.mutable.Stack -import Chisel._ + +import chisel3._ +import chisel3.util._ class ChiselStack(val depth: Int) extends Module { val io = new Bundle { -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/test/scala/chiselTests/Stack.scala | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/test/scala/chiselTests/Stack.scala') diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 683c5224..440228c9 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -12,8 +12,8 @@ class ChiselStack(val depth: Int) extends Module { val push = Input(Bool()) val pop = Input(Bool()) val en = Input(Bool()) - val dataIn = Input(UInt(32)) - val dataOut = Output(UInt(32)) + val dataIn = Input(UInt.width(32)) + val dataOut = Output(UInt.width(32)) }) val stack_mem = Mem(depth, UInt(width = 32)) @@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module { val out = Reg(init = UInt(0, width = 32)) when (io.en) { - when(io.push && (sp < UInt(depth))) { + when(io.push && (sp < UInt.Lit(depth))) { stack_mem(sp) := io.dataIn - sp := sp +% UInt(1) - } .elsewhen(io.pop && (sp > UInt(0))) { - sp := sp -% UInt(1) + sp := sp +% UInt.Lit(1) + } .elsewhen(io.pop && (sp > UInt.Lit(0))) { + sp := sp -% UInt.Lit(1) } - when (sp > UInt(0)) { - out := stack_mem(sp -% UInt(1)) + when (sp > UInt.Lit(0)) { + out := stack_mem(sp -% UInt.Lit(1)) } } io.dataOut := out -- cgit v1.2.3 From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 17:08:55 -0700 Subject: More literal/width rangling. --- src/test/scala/chiselTests/Stack.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Stack.scala') diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 440228c9..0c84e62a 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -16,7 +16,7 @@ class ChiselStack(val depth: Int) extends Module { val dataOut = Output(UInt.width(32)) }) - val stack_mem = Mem(depth, UInt(width = 32)) + val stack_mem = Mem(depth, UInt.width(32)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) val out = Reg(init = UInt(0, width = 32)) -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/test/scala/chiselTests/Stack.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/test/scala/chiselTests/Stack.scala') diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 0c84e62a..a72af928 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -21,14 +21,14 @@ class ChiselStack(val depth: Int) extends Module { val out = Reg(init = UInt(0, width = 32)) when (io.en) { - when(io.push && (sp < UInt.Lit(depth))) { + when(io.push && (sp < UInt(depth))) { stack_mem(sp) := io.dataIn - sp := sp +% UInt.Lit(1) - } .elsewhen(io.pop && (sp > UInt.Lit(0))) { - sp := sp -% UInt.Lit(1) + sp := sp +% UInt(1) + } .elsewhen(io.pop && (sp > UInt(0))) { + sp := sp -% UInt(1) } - when (sp > UInt.Lit(0)) { - out := stack_mem(sp -% UInt.Lit(1)) + when (sp > UInt(0)) { + out := stack_mem(sp -% UInt(1)) } } io.dataOut := out -- cgit v1.2.3