From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 21 Jun 2016 09:17:30 -0700 Subject: New Module, IO, Input/Output wrapping. --- src/test/scala/chiselTests/SIntOps.scala | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'src/test/scala/chiselTests/SIntOps.scala') diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 0835fb4d..934c66a4 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -5,24 +5,24 @@ import Chisel._ import Chisel.testers.BasicTester class SIntOps extends Module { - val io = new Bundle { - val a = SInt(INPUT, 16) - val b = SInt(INPUT, 16) - val addout = SInt(OUTPUT, 16) - val subout = SInt(OUTPUT, 16) - val timesout = SInt(OUTPUT, 16) - val divout = SInt(OUTPUT, 16) - val modout = SInt(OUTPUT, 16) - val lshiftout = SInt(OUTPUT, 16) - val rshiftout = SInt(OUTPUT, 16) - val lessout = Bool(OUTPUT) - val greatout = Bool(OUTPUT) - val eqout = Bool(OUTPUT) - val noteqout = Bool(OUTPUT) - val lesseqout = Bool(OUTPUT) - val greateqout = Bool(OUTPUT) - val negout = SInt(OUTPUT, 16) - } + val io = IO(new Bundle { + val a = Input(SInt(16)) + val b = Input(SInt(16)) + val addout = Output(SInt(16)) + val subout = Output(SInt(16)) + val timesout = Output(SInt(16)) + val divout = Output(SInt(16)) + val modout = Output(SInt(16)) + val lshiftout = Output(SInt(16)) + val rshiftout = Output(SInt(16)) + val lessout = Output(Bool()) + val greatout = Output(Bool()) + val eqout = Output(Bool()) + val noteqout = Output(Bool()) + val lesseqout = Output(Bool()) + val greateqout = Output(Bool()) + val negout = Output(SInt(16)) + }) val a = io.a val b = io.b -- cgit v1.2.3 From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/test/scala/chiselTests/SIntOps.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests/SIntOps.scala') diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index 0835fb4d..6cd013f1 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -1,8 +1,9 @@ // See LICENSE for license details. package chiselTests -import Chisel._ -import Chisel.testers.BasicTester + +import chisel3._ +import chisel3.testers.BasicTester class SIntOps extends Module { val io = new Bundle { -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/test/scala/chiselTests/SIntOps.scala | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'src/test/scala/chiselTests/SIntOps.scala') diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index a98edf9b..d827c096 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -7,22 +7,22 @@ import chisel3.testers.BasicTester class SIntOps extends Module { val io = IO(new Bundle { - val a = Input(SInt(16)) - val b = Input(SInt(16)) - val addout = Output(SInt(16)) - val subout = Output(SInt(16)) - val timesout = Output(SInt(16)) - val divout = Output(SInt(16)) - val modout = Output(SInt(16)) - val lshiftout = Output(SInt(16)) - val rshiftout = Output(SInt(16)) + val a = Input(SInt.width(16)) + val b = Input(SInt.width(16)) + val addout = Output(SInt.width(16)) + val subout = Output(SInt.width(16)) + val timesout = Output(SInt.width(16)) + val divout = Output(SInt.width(16)) + val modout = Output(SInt.width(16)) + val lshiftout = Output(SInt.width(16)) + val rshiftout = Output(SInt.width(16)) val lessout = Output(Bool()) val greatout = Output(Bool()) val eqout = Output(Bool()) val noteqout = Output(Bool()) val lesseqout = Output(Bool()) val greateqout = Output(Bool()) - val negout = Output(SInt(16)) + val negout = Output(SInt.width(16)) }) val a = io.a @@ -32,9 +32,9 @@ class SIntOps extends Module { io.subout := a -% b // TODO: //io.timesout := (a * b)(15, 0) - //io.divout := a / Mux(b === SInt(0), SInt(1), b) + //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b) //io.divout := (a / b)(15, 0) - //io.modout := SInt(0) + //io.modout := SInt.Lit(0) //io.lshiftout := (a << 12)(15, 0) // (a << ub(3, 0))(15, 0).toSInt io.rshiftout := (a >> 8) // (a >> ub).toSInt io.lessout := a < b @@ -44,7 +44,7 @@ class SIntOps extends Module { io.lesseqout := a <= b io.greateqout := a >= b // io.negout := -a(15, 0).toSInt - io.negout := (SInt(0) -% a) + io.negout := (SInt.Lit(0) -% a) } /* -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/test/scala/chiselTests/SIntOps.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests/SIntOps.scala') diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala index d827c096..392c4803 100644 --- a/src/test/scala/chiselTests/SIntOps.scala +++ b/src/test/scala/chiselTests/SIntOps.scala @@ -32,9 +32,9 @@ class SIntOps extends Module { io.subout := a -% b // TODO: //io.timesout := (a * b)(15, 0) - //io.divout := a / Mux(b === SInt.Lit(0), SInt.Lit(1), b) + //io.divout := a / Mux(b === SInt(0), SInt(1), b) //io.divout := (a / b)(15, 0) - //io.modout := SInt.Lit(0) + //io.modout := SInt(0) //io.lshiftout := (a << 12)(15, 0) // (a << ub(3, 0))(15, 0).toSInt io.rshiftout := (a >> 8) // (a >> ub).toSInt io.lessout := a < b @@ -44,7 +44,7 @@ class SIntOps extends Module { io.lesseqout := a <= b io.greateqout := a >= b // io.negout := -a(15, 0).toSInt - io.negout := (SInt.Lit(0) -% a) + io.negout := (SInt(0) -% a) } /* -- cgit v1.2.3