From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/test/scala/chiselTests/Reg.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests/Reg.scala') diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index f2620d88..391dd7de 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -3,8 +3,9 @@ package chiselTests import org.scalatest._ -import Chisel._ -import Chisel.testers.BasicTester +import chisel3._ +import chisel3.core.DataMirror +import chisel3.testers.BasicTester class RegSpec extends ChiselFlatSpec { "A Reg" should "throw an exception if not given any parameters" in { -- cgit v1.2.3 From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 19 Jul 2016 15:08:22 -0700 Subject: Incorporate connection logic. Compiles but fails tests. --- src/test/scala/chiselTests/Reg.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src/test/scala/chiselTests/Reg.scala') diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 391dd7de..0caf6315 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,20 +16,20 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20)) - reg.width.get should be (2) + val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20)) + reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } } "A Reg" should "be of unknown width if outType is not specified and width is not forced" in { class RegUnknownWidthTester extends BasicTester { - val reg1 = Reg(next=UInt(width=3), init=UInt(20)) - reg1.width.known should be (false) - val reg2 = Reg(init=UInt(20)) - reg2.width.known should be (false) - val reg3 = Reg(next=UInt(width=3), init=UInt(width=5)) - reg3.width.known should be (false) + val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U) + DataMirror.widthOf(reg1).known should be (false) + val reg2 = Reg(init=20.U) + DataMirror.widthOf(reg2).known should be (false) + val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U) + DataMirror.widthOf(reg3).known should be (false) } elaborate { new RegUnknownWidthTester } } @@ -37,7 +37,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in { class RegForcedWidthTester extends BasicTester { val reg2 = Reg(init=UInt(20, width=7)) - reg2.width.get should be (7) + reg2.getWidth should be (7) } elaborate{ new RegForcedWidthTester } } -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/test/scala/chiselTests/Reg.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Reg.scala') diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 0caf6315..5d4bd18d 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20)) + val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } -- cgit v1.2.3 From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 17:08:55 -0700 Subject: More literal/width rangling. --- src/test/scala/chiselTests/Reg.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests/Reg.scala') diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 5d4bd18d..8b9016b1 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt.Lit(20)) + val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } @@ -24,11 +24,11 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of unknown width if outType is not specified and width is not forced" in { class RegUnknownWidthTester extends BasicTester { - val reg1 = Reg(next=Wire(UInt(width=3)), init=20.U) + val reg1 = Reg(next=Wire(UInt.width(3)), init=20.U) DataMirror.widthOf(reg1).known should be (false) val reg2 = Reg(init=20.U) DataMirror.widthOf(reg2).known should be (false) - val reg3 = Reg(next=Wire(UInt(width=3)), init=5.U) + val reg3 = Reg(next=Wire(UInt.width(3)), init=5.U) DataMirror.widthOf(reg3).known should be (false) } elaborate { new RegUnknownWidthTester } -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/test/scala/chiselTests/Reg.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Reg.scala') diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala index 8b9016b1..b66d7cb4 100644 --- a/src/test/scala/chiselTests/Reg.scala +++ b/src/test/scala/chiselTests/Reg.scala @@ -16,7 +16,7 @@ class RegSpec extends ChiselFlatSpec { "A Reg" should "be of the same type and width as outType, if specified" in { class RegOutTypeWidthTester extends BasicTester { - val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt.Lit(20)) + val reg = Reg(t=UInt.width(2), next=Wire(UInt.width(3)), init=UInt(20)) reg.getWidth should be (2) } elaborate{ new RegOutTypeWidthTester } -- cgit v1.2.3