From 3131c0daad41dea78bede4517669e376c41a325a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 10 Jan 2022 10:39:52 -0800
Subject: Apply scalafmt

Command:
sbt scalafmtAll
---
 src/test/scala/chiselTests/RebindingSpec.scala | 28 +++++++++++++++-----------
 1 file changed, 16 insertions(+), 12 deletions(-)

(limited to 'src/test/scala/chiselTests/RebindingSpec.scala')

diff --git a/src/test/scala/chiselTests/RebindingSpec.scala b/src/test/scala/chiselTests/RebindingSpec.scala
index 808b1137..5dc0589e 100644
--- a/src/test/scala/chiselTests/RebindingSpec.scala
+++ b/src/test/scala/chiselTests/RebindingSpec.scala
@@ -7,22 +7,26 @@ import chisel3.stage.ChiselStage
 
 class RebindingSpec extends ChiselFlatSpec with Utils {
   "Rebinding a literal" should "fail" in {
-    a [BindingException] should be thrownBy extractCause[BindingException] {
-      ChiselStage.elaborate { new Module {
-        val io = IO(new Bundle {
-          val a = 4.U
-        })
-      } }
+    a[BindingException] should be thrownBy extractCause[BindingException] {
+      ChiselStage.elaborate {
+        new Module {
+          val io = IO(new Bundle {
+            val a = 4.U
+          })
+        }
+      }
     }
   }
 
   "Rebinding a hardware type" should "fail" in {
-    a [BindingException] should be thrownBy extractCause[BindingException] {
-      ChiselStage.elaborate { new Module {
-        val io = IO(new Bundle {
-          val a = Reg(UInt(32.W))
-        })
-      } }
+    a[BindingException] should be thrownBy extractCause[BindingException] {
+      ChiselStage.elaborate {
+        new Module {
+          val io = IO(new Bundle {
+            val a = Reg(UInt(32.W))
+          })
+        }
+      }
     }
   }
 }
-- 
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