From 4c512593fb5688f3de502ba1ed70681a0802b6c9 Mon Sep 17 00:00:00 2001
From: edwardcwang
Date: Tue, 19 Feb 2019 16:14:39 -0800
Subject: Mainline Chisel multi-clock functionality (#1013)

Close #1009---
 src/test/scala/chiselTests/RawModuleSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/RawModuleSpec.scala')

diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
index b864a669..88b53457 100644
--- a/src/test/scala/chiselTests/RawModuleSpec.scala
+++ b/src/test/scala/chiselTests/RawModuleSpec.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{RawModule, withClockAndReset}
+import chisel3.experimental.RawModule
 import chisel3.testers.BasicTester
 
 class UnclockedPlusOne extends RawModule {
-- 
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