From 3131c0daad41dea78bede4517669e376c41a325a Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 10 Jan 2022 10:39:52 -0800
Subject: Apply scalafmt

Command:
sbt scalafmtAll
---
 src/test/scala/chiselTests/RawModuleSpec.scala | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'src/test/scala/chiselTests/RawModuleSpec.scala')

diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
index 3d678d1f..95687e82 100644
--- a/src/test/scala/chiselTests/RawModuleSpec.scala
+++ b/src/test/scala/chiselTests/RawModuleSpec.scala
@@ -7,7 +7,7 @@ import chisel3.stage.ChiselStage
 import chisel3.testers.BasicTester
 
 class UnclockedPlusOne extends RawModule {
-  val in  = IO(Input(UInt(32.W)))
+  val in = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
 
   out := in + 1.asUInt
@@ -22,14 +22,14 @@ class RawModuleTester extends BasicTester {
 
 class PlusOneModule extends Module {
   val io = IO(new Bundle {
-    val in  = Input(UInt(32.W))
+    val in = Input(UInt(32.W))
     val out = Output(UInt(32.W))
   })
   io.out := io.in + 1.asUInt
 }
 
 class RawModuleWithImplicitModule extends RawModule {
-  val in  = IO(Input(UInt(32.W)))
+  val in = IO(Input(UInt(32.W)))
   val out = IO(Output(UInt(32.W)))
   val clk = IO(Input(Clock()))
   val rst = IO(Input(Bool()))
@@ -72,7 +72,6 @@ class RawModuleSpec extends ChiselFlatSpec with Utils {
     assertTesterPasses({ new ImplicitModuleInRawModuleTester })
   }
 
-
   "ImplicitModule directly in a RawModule" should "fail" in {
     intercept[chisel3.internal.ChiselException] {
       extractCause[ChiselException] {
-- 
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