From bc05b7dadbd875c5a1ffb1448c36fcdb429386ab Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Sun, 2 Apr 2017 18:29:17 -0700
Subject: Make Module instantiations draw clock from Builder instead of parent
 (#568)

Fixes #567---
 src/test/scala/chiselTests/MultiClockSpec.scala | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 23c984b5..ada0b9b0 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -27,6 +27,31 @@ class ClockDividerTest extends BasicTester {
   }
 }
 
+class MultiClockSubModuleTest extends BasicTester {
+  class SubModule extends Module {
+    val io = IO(new Bundle {
+      val out = Output(UInt())
+    })
+    val (cycle, _) = Counter(true.B, 10)
+    io.out := cycle
+  }
+
+  val (cycle, done) = Counter(true.B, 10)
+  val cDiv = RegInit(true.B) // start with falling edge to simplify clock relationship assert
+  cDiv := !cDiv
+
+  val otherClock = cDiv.asClock
+  val otherReset = cycle < 3.U
+
+  val inst = withClockAndReset(otherClock, otherReset) { Module(new SubModule) }
+
+  when (done) {
+    // The counter in inst should come out of reset later and increment at half speed
+    assert(inst.io.out === 3.U)
+    stop()
+  }
+}
+
 /** Test withReset changing the reset of a Reg */
 class WithResetTest extends BasicTester {
   val reset2 = Wire(init = false.B)
@@ -108,6 +133,10 @@ class MultiClockSpec extends ChiselFlatSpec {
     assertTesterPasses(new WithResetTest)
   }
 
+  it should "scope the clock and reset of Modules" in {
+    assertTesterPasses(new MultiClockSubModuleTest)
+  }
+
   it should "return like a normal Scala block" in {
     elaborate(new BasicTester {
       assert(withReset(this.reset) { 5 } == 5)
-- 
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