From 6e03f63d525aac0bdf4a59b6fe66a0b4d5a3a25a Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 16 Jun 2020 11:59:15 -0400 Subject: Use ChiselStage in Tests This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge --- src/test/scala/chiselTests/MultiClockSpec.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala') diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 770a9e9a..1a71570d 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -5,6 +5,7 @@ package chiselTests import chisel3._ import chisel3.util.Counter import chisel3.testers.BasicTester +import chisel3.stage.ChiselStage /** Multi-clock test of a Reg using a different clock via withClock */ class ClockDividerTest extends BasicTester { @@ -123,7 +124,7 @@ class MultiClockSpec extends ChiselFlatSpec { } it should "return like a normal Scala block" in { - elaborate(new BasicTester { + ChiselStage.elaborate(new BasicTester { assert(withClock(this.clock) { 5 } == 5) }) } @@ -137,7 +138,7 @@ class MultiClockSpec extends ChiselFlatSpec { } it should "return like a normal Scala block" in { - elaborate(new BasicTester { + ChiselStage.elaborate(new BasicTester { assert(withReset(this.reset) { 5 } == 5) }) } @@ -155,7 +156,7 @@ class MultiClockSpec extends ChiselFlatSpec { } "withClockAndReset" should "return like a normal Scala block" in { - elaborate(new BasicTester { + ChiselStage.elaborate(new BasicTester { assert(withClockAndReset(this.clock, this.reset) { 5 } == 5) }) } -- cgit v1.2.3