From 0a17d89fe76c11efadc3d0f90dc1d93a690d861a Mon Sep 17 00:00:00 2001
From: chick
Date: Tue, 17 Dec 2019 13:26:08 -0800
Subject: This adds a mechanism for the unittests to be run with the
 TreadleBackend This mechanism is not enabled and should not change the
 behavior of existing tests A following PR will deliver a switch that will
 allow changing the backend. The reasons for this PR - Treadle tests run much
 faster, enabling quicker debugging and CI cycles - This will help ensure
 fidelity of Treadle to the Verilator backend

A few tests are marked as verilator only due to black box limitations

Change treadle to a direct dependency

I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that
regular compile have access to treadle

Oops, made treadle the default

A number of changes in response to @ducky64 review
- made backend check clearer and add error handling for multiple backends specified
- Fixed duplicate TargetDirAnnotation uses in Treadle backend
- Cleaned up BlackBox test formatting
- Undid unnecessary debugging changes from Counter
- Undid .gitignore change, that should be on another PR

A number of changes in response to @ducky64 review
- Undid debugging changes made to BitWiseOps
---
 src/test/scala/chiselTests/MultiClockSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 1a71570d..8b7fddb0 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -120,7 +120,7 @@ class MultiClockSpec extends ChiselFlatSpec {
   }
 
   it should "scope ports of memories" in {
-    assertTesterPasses(new MultiClockMemTest)
+    assertTesterPasses(new MultiClockMemTest, annotations = TesterDriver.verilatorOnly)
   }
 
   it should "return like a normal Scala block" in {
-- 
cgit v1.2.3


From 3694b092830ac0a8d1e5a6dfe9a65d88420c1962 Mon Sep 17 00:00:00 2001
From: chick
Date: Mon, 29 Jun 2020 10:44:13 -0700
Subject: - A few final fixes after the rebase

---
 src/test/scala/chiselTests/MultiClockSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')

diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 8b7fddb0..0b9497b8 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.Counter
-import chisel3.testers.BasicTester
+import chisel3.testers.{BasicTester, TesterDriver}
 import chisel3.stage.ChiselStage
 
 /** Multi-clock test of a Reg using a different clock via withClock */
-- 
cgit v1.2.3