From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 src/test/scala/chiselTests/MultiAssign.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests/MultiAssign.scala')

diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 397ea4c2..fbe57da5 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,10 +9,10 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
-  val countOnClockCycles = Bool(true)
+  val countOnClockCycles = true.B
   val (cnt, wrap) = Counter(countOnClockCycles,2)
 
-  val test = Wire(UInt.width(4))
+  val test = Wire(UInt(4.W))
   assert(test === 7.U)  // allow read references before assign references
 
   test := 13.U
-- 
cgit v1.2.3