From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 21 Jun 2016 09:17:30 -0700 Subject: New Module, IO, Input/Output wrapping. --- src/test/scala/chiselTests/Module.scala | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 88ba795b..ba251916 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -4,20 +4,20 @@ package chiselTests import Chisel._ class SimpleIO extends Bundle { - val in = UInt(INPUT, 32) - val out = UInt(OUTPUT, 32) + val in = Input(UInt(32)) + val out = Output(UInt(32)) } class PlusOne extends Module { - val io = new SimpleIO + val io = IO(new SimpleIO) io.out := io.in + UInt(1) } class ModuleVec(val n: Int) extends Module { - val io = new Bundle { - val ins = Vec(n, UInt(INPUT, 32)) - val outs = Vec(n, UInt(OUTPUT, 32)) - } + val io = IO(new Bundle { + val ins = Input(Vec(n, UInt(32))) + val outs = Output(Vec(n, UInt(32))) + }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { pluses(i).in := io.ins(i) @@ -39,8 +39,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { */ class ModuleWire extends Module { - val io = new SimpleIO - val inc = Wire(Module(new PlusOne).io) + val io = IO(new SimpleIO) + val inc = Wire(Module(new PlusOne).io.newType) inc.in := io.in io.out := inc.out } @@ -57,10 +57,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) { */ class ModuleWhen extends Module { - val io = new Bundle { + val io = IO(new Bundle { val s = new SimpleIO val en = Bool() - } + }) when(io.en) { val inc = Module(new PlusOne).io inc.in := io.s.in -- cgit v1.2.3 From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 6 Jul 2016 09:31:47 -0700 Subject: Update Chisel -> chisel3 references. --- src/test/scala/chiselTests/Module.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 88ba795b..23788b72 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -1,7 +1,8 @@ // See LICENSE for license details. package chiselTests -import Chisel._ + +import chisel3._ class SimpleIO extends Bundle { val in = UInt(INPUT, 32) -- cgit v1.2.3 From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 19 Jul 2016 15:08:22 -0700 Subject: Incorporate connection logic. Compiles but fails tests. --- src/test/scala/chiselTests/Module.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 7c0bc40e..f1608d5b 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { class ModuleWire extends Module { val io = IO(new SimpleIO) - val inc = Wire(Module(new PlusOne).io.newType) + val inc = Wire(Module(new PlusOne).io.cloneType) inc.in := io.in io.out := inc.out } -- cgit v1.2.3 From 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 13:28:15 -0700 Subject: Compile ok. Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x) --- src/test/scala/chiselTests/Module.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index f1608d5b..857aeda3 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -11,7 +11,7 @@ class SimpleIO extends Bundle { class PlusOne extends Module { val io = IO(new SimpleIO) - io.out := io.in + UInt(1) + io.out := io.in + 1.asUInt } class ModuleVec(val n: Int) extends Module { -- cgit v1.2.3 From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 20 Jul 2016 14:49:35 -0700 Subject: Distinguish between ?Int.Lit and ?Int.width --- src/test/scala/chiselTests/Module.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 857aeda3..59451a2b 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -5,8 +5,8 @@ package chiselTests import chisel3._ class SimpleIO extends Bundle { - val in = Input(UInt(32)) - val out = Output(UInt(32)) + val in = Input(UInt.width(32)) + val out = Output(UInt.width(32)) } class PlusOne extends Module { @@ -16,8 +16,8 @@ class PlusOne extends Module { class ModuleVec(val n: Int) extends Module { val io = IO(new Bundle { - val ins = Input(Vec(n, UInt(32))) - val outs = Output(Vec(n, UInt(32))) + val ins = Input(Vec(n, UInt.Lit(32))) + val outs = Output(Vec(n, UInt.Lit(32))) }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { -- cgit v1.2.3 From 7c9043859994b32bb07d2fce4ae61a7a3362a1b3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 21 Jul 2016 17:12:06 -0700 Subject: Introduce chiselCloneType to distinguish from cloneType. Still fails one test - DirectionSpec in Direction.scala --- src/test/scala/chiselTests/Module.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 59451a2b..26953f5f 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { class ModuleWire extends Module { val io = IO(new SimpleIO) - val inc = Wire(Module(new PlusOne).io.cloneType) + val inc = Wire(Module(new PlusOne).io.chiselCloneType) inc.in := io.in io.out := inc.out } -- cgit v1.2.3 From 7aa05590382b0528799ad5e9f1318ce42e409793 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 14:06:51 -0700 Subject: Minimize differences with master. Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. --- src/test/scala/chiselTests/Module.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 26953f5f..7a4050db 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -16,8 +16,8 @@ class PlusOne extends Module { class ModuleVec(val n: Int) extends Module { val io = IO(new Bundle { - val ins = Input(Vec(n, UInt.Lit(32))) - val outs = Output(Vec(n, UInt.Lit(32))) + val ins = Input(Vec(n, UInt(32))) + val outs = Output(Vec(n, UInt(32))) }) val pluses = Vec.fill(n){ Module(new PlusOne).io } for (i <- 0 until n) { -- cgit v1.2.3 From 6df3a785f8abe706838bc5b4b35c3374b6512f96 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 12:17:48 -0700 Subject: Pass compileOptions as an implicit Module parameter. --- src/test/scala/chiselTests/Module.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 7a4050db..8d72fc44 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.NotStrict.NotStrictCompileOptions class SimpleIO extends Bundle { val in = Input(UInt.width(32)) -- cgit v1.2.3 From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 13:45:05 -0700 Subject: Rename CompileOptions implicit objects. --- src/test/scala/chiselTests/Module.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 8d72fc44..1f0ab084 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -3,7 +3,7 @@ package chiselTests import chisel3._ -import chisel3.NotStrict.NotStrictCompileOptions +import chisel3.NotStrict.CompileOptions class SimpleIO extends Bundle { val in = Input(UInt.width(32)) -- cgit v1.2.3 From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 11:44:09 -0700 Subject: Massive rename of CompileOptions. Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used. --- src/test/scala/chiselTests/Module.scala | 1 - 1 file changed, 1 deletion(-) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 1f0ab084..7a4050db 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.NotStrict.CompileOptions class SimpleIO extends Bundle { val in = Input(UInt.width(32)) -- cgit v1.2.3