From dafdeab614a5106dac4d80e147fdbc2770053e1b Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 3 Oct 2018 16:15:37 -0700
Subject: Add DataMirror.modulePorts (#901)

---
 src/test/scala/chiselTests/Module.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/test/scala/chiselTests/Module.scala')

diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 5f2927dd..968e7578 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -126,4 +126,16 @@ class ModuleSpec extends ChiselPropSpec {
       assert(checkModule(this))
     })
   }
+  property("DataMirror.modulePorts should work") {
+    elaborate(new Module {
+      val io = IO(new Bundle { })
+      val m = Module(new chisel3.experimental.MultiIOModule {
+        val a = IO(UInt(8.W))
+        val b = IO(Bool())
+      })
+      assert(chisel3.experimental.DataMirror.modulePorts(m) == Seq(
+          "clock" -> m.clock, "reset" -> m.reset,
+          "a" -> m.a, "b" -> m.b))
+    })
+  }
 }
-- 
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