From 556ce39b2b33787407a3634f775b6a2a9da086c8 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 8 Feb 2022 17:11:01 +0000 Subject: Overload getVerilogString to accept arguments (#2401) (#2402) (cherry picked from commit b55dc36d4edd1d22db37616235c003c89d68d29b) Co-authored-by: Carlos Eduardo --- src/test/scala/chiselTests/Module.scala | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/test/scala/chiselTests/Module.scala') diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 13dbe1e9..b0fece3b 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -18,6 +18,8 @@ class SimpleIO extends Bundle { class PlusOne extends Module { val io = IO(new SimpleIO) + val myReg = RegInit(0.U(8.W)) + dontTouch(myReg) io.out := io.in + 1.asUInt } @@ -267,6 +269,13 @@ class ModuleSpec extends ChiselPropSpec with Utils { property("getVerilogString(new PlusOne() should produce a valid Verilog string") { val s = getVerilogString(new PlusOne()) assert(s.contains("assign io_out = io_in + 32'h1")) + assert(s.contains("RANDOMIZE_REG_INIT")) + } + + property("getVerilogString(new PlusOne() should produce a valid Verilog string with arguments") { + val s = getVerilogString(new PlusOne(), Array("--emission-options=disableRegisterRandomization")) + assert(s.contains("assign io_out = io_in + 32'h1")) + assert(!s.contains("RANDOMIZE_REG_INIT")) } property("emitVerilog((new PlusOne()..) shall produce a valid Verilog file in a subfolder") { -- cgit v1.2.3