From 4c512593fb5688f3de502ba1ed70681a0802b6c9 Mon Sep 17 00:00:00 2001
From: edwardcwang
Date: Tue, 19 Feb 2019 16:14:39 -0800
Subject: Mainline Chisel multi-clock functionality (#1013)

Close #1009---
 src/test/scala/chiselTests/Module.scala | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/test/scala/chiselTests/Module.scala')

diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index b3d1899c..a973412e 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{withClock, withReset}
 
 class SimpleIO extends Bundle {
   val in  = Input(UInt(32.W))
-- 
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