From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 14:49:35 -0700
Subject: Distinguish between ?Int.Lit and ?Int.width

---
 src/test/scala/chiselTests/Module.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/test/scala/chiselTests/Module.scala')

diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 857aeda3..59451a2b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,8 +5,8 @@ package chiselTests
 import chisel3._
 
 class SimpleIO extends Bundle {
-  val in  = Input(UInt(32))
-  val out = Output(UInt(32))
+  val in  = Input(UInt.width(32))
+  val out = Output(UInt.width(32))
 }
 
 class PlusOne extends Module {
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt(32)))
-    val outs = Output(Vec(n, UInt(32)))
+    val ins  = Input(Vec(n, UInt.Lit(32)))
+    val outs = Output(Vec(n, UInt.Lit(32)))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
-- 
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