From 741761cfbac8d8b7e297666c66d91cb773a6f109 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Thu, 10 Mar 2022 01:10:30 +0000 Subject: Emit FIRRTL bulkconnects whenever possible (#2381) (#2440) Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung Co-authored-by: Jack Koenig (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig --- src/test/scala/chiselTests/MixedVecSpec.scala | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/test/scala/chiselTests/MixedVecSpec.scala') diff --git a/src/test/scala/chiselTests/MixedVecSpec.scala b/src/test/scala/chiselTests/MixedVecSpec.scala index 16efafd4..ee19d653 100644 --- a/src/test/scala/chiselTests/MixedVecSpec.scala +++ b/src/test/scala/chiselTests/MixedVecSpec.scala @@ -280,4 +280,20 @@ class MixedVecSpec extends ChiselPropSpec with Utils { }) } } + + property("MixedVec connections should emit FIRRTL bulk connects when possible") { + val chirrtl = ChiselStage.emitChirrtl(new Module { + val io = IO(new Bundle { + val inMono = Input(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W)))) + val outMono = Output(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W)))) + val inBi = Input(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W)))) + val outBi = Output(MixedVec(Seq(UInt(8.W), UInt(16.W), UInt(4.W), UInt(7.W)))) + }) + // Explicit upcast avoids weird issue where Scala 2.12 overloading resolution calls version of := accepting Seq[T] instead of normal Data version + io.outMono := (io.inMono: Data) + io.outBi <> io.inBi + }) + chirrtl should include("io.outMono <= io.inMono @[MixedVecSpec.scala") + chirrtl should include("io.outBi <= io.inBi @[MixedVecSpec.scala") + } } -- cgit v1.2.3