From d675043717593fb7e96fb0f1952debbeb7f20a57 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 21 Jun 2016 09:17:30 -0700
Subject: New Module, IO, Input/Output wrapping.

---
 src/test/scala/chiselTests/LFSR16.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/test/scala/chiselTests/LFSR16.scala')

diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..54144bea 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -5,10 +5,10 @@ import Chisel._
 import Chisel.testers.BasicTester
 
 class LFSR16 extends Module {
-  val io = new Bundle {
-    val inc = Bool(INPUT)
-    val out = UInt(OUTPUT, 16)
-  }
+  val io = IO(new Bundle {
+    val inc = Input(Bool())
+    val out = Output(UInt(16))
+  })
   val res = Reg(init = UInt(1, 16))
   when (io.inc) {
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 src/test/scala/chiselTests/LFSR16.scala | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/test/scala/chiselTests/LFSR16.scala')

diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..a1699441 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -1,8 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LFSR16 extends Module {
   val io = new Bundle {
@@ -34,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 }
 */
 
-//TODO: Use chisel.util version instead?
+//TODO: Use chisel3.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
 
-- 
cgit v1.2.3


From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 14:49:35 -0700
Subject: Distinguish between ?Int.Lit and ?Int.width

---
 src/test/scala/chiselTests/LFSR16.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/test/scala/chiselTests/LFSR16.scala')

diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 2d5e7f3e..b13b67e3 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -9,7 +9,7 @@ import chisel3.util._
 class LFSR16 extends Module {
   val io = IO(new Bundle {
     val inc = Input(Bool())
-    val out = Output(UInt(16))
+    val out = Output(UInt.width(16))
   })
   val res = Reg(init = UInt(1, 16))
   when (io.inc) {
-- 
cgit v1.2.3