From e09a09e3f4e5d6d8650b1db4add96c0a5b09e8ca Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 25 Jul 2016 16:36:06 -0700 Subject: Enable current (chisel2-style) compatibility mode. --- src/test/scala/chiselTests/IOCompatibility.scala | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 src/test/scala/chiselTests/IOCompatibility.scala (limited to 'src/test/scala/chiselTests/IOCompatibility.scala') diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala new file mode 100644 index 00000000..b904d77e --- /dev/null +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -0,0 +1,45 @@ +// See LICENSE for license details. + +package chiselTests + +import chisel3._ + +class IOCSimpleIO extends Bundle { + val in = UInt(INPUT, 32) + val out = UInt(OUTPUT, 32) +} + +class IOCPlusOne extends Module { + val io = new IOCSimpleIO + io.out := io.in + UInt(1) +} + +class IOCModuleVec(val n: Int) extends Module { + val io = new Bundle { + val ins = Vec(n, UInt(INPUT, 32)) + val outs = Vec(n, UInt(OUTPUT, 32)) + } + val pluses = Vec.fill(n){ Module(new IOCPlusOne).io } + for (i <- 0 until n) { + pluses(i).in := io.ins(i) + io.outs(i) := pluses(i).out + } +} + +class IOCModuleWire extends Module { + val io = new IOCSimpleIO + val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType) + inc.in := io.in + io.out := inc.out +} + +class IOCompatibilitySpec extends ChiselPropSpec { + + property("IOCModuleVec should elaborate") { + elaborate { new IOCModuleVec(2) } + } + + property("IOCModuleWire should elaborate") { + elaborate { new IOCModuleWire } + } +} -- cgit v1.2.3 From 138329479914ac37b49a5a44841dc1de2929dca5 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 27 Jul 2016 10:36:55 -0700 Subject: More compatibility fixes --- src/test/scala/chiselTests/IOCompatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/IOCompatibility.scala') diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index b904d77e..edbd3d09 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -2,7 +2,7 @@ package chiselTests -import chisel3._ +import Chisel._ class IOCSimpleIO extends Bundle { val in = UInt(INPUT, 32) -- cgit v1.2.3 From 6df3a785f8abe706838bc5b4b35c3374b6512f96 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 12:17:48 -0700 Subject: Pass compileOptions as an implicit Module parameter. --- src/test/scala/chiselTests/IOCompatibility.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'src/test/scala/chiselTests/IOCompatibility.scala') diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index edbd3d09..c247973d 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -3,6 +3,7 @@ package chiselTests import Chisel._ +import chisel3.NotStrict.NotStrictCompileOptions class IOCSimpleIO extends Bundle { val in = UInt(INPUT, 32) -- cgit v1.2.3 From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 29 Aug 2016 13:45:05 -0700 Subject: Rename CompileOptions implicit objects. --- src/test/scala/chiselTests/IOCompatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/IOCompatibility.scala') diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index c247973d..aa3bd962 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -3,7 +3,7 @@ package chiselTests import Chisel._ -import chisel3.NotStrict.NotStrictCompileOptions +import chisel3.NotStrict.CompileOptions class IOCSimpleIO extends Bundle { val in = UInt(INPUT, 32) -- cgit v1.2.3 From 8002f7ac6731b1da5e0d8e7b1536995a23878037 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 30 Aug 2016 13:45:37 -0700 Subject: Make compileOptions in the Chisel package effective. Remove references to the Chisel package in favor of explicit chisel3 imports in tests, --- src/test/scala/chiselTests/IOCompatibility.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/test/scala/chiselTests/IOCompatibility.scala') diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index aa3bd962..d100df2b 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -2,7 +2,7 @@ package chiselTests -import Chisel._ +import chisel3._ import chisel3.NotStrict.CompileOptions class IOCSimpleIO extends Bundle { -- cgit v1.2.3 From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 29 Sep 2016 11:44:09 -0700 Subject: Massive rename of CompileOptions. Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used. --- src/test/scala/chiselTests/IOCompatibility.scala | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'src/test/scala/chiselTests/IOCompatibility.scala') diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala index d100df2b..7bf3dded 100644 --- a/src/test/scala/chiselTests/IOCompatibility.scala +++ b/src/test/scala/chiselTests/IOCompatibility.scala @@ -3,23 +3,22 @@ package chiselTests import chisel3._ -import chisel3.NotStrict.CompileOptions class IOCSimpleIO extends Bundle { - val in = UInt(INPUT, 32) - val out = UInt(OUTPUT, 32) + val in = Input(UInt(width=32)) + val out = Output(UInt(width=32)) } class IOCPlusOne extends Module { - val io = new IOCSimpleIO + val io = IO(new IOCSimpleIO) io.out := io.in + UInt(1) } class IOCModuleVec(val n: Int) extends Module { - val io = new Bundle { - val ins = Vec(n, UInt(INPUT, 32)) - val outs = Vec(n, UInt(OUTPUT, 32)) - } + val io = IO(new Bundle { + val ins = Vec(n, Input(UInt(width=32))) + val outs = Vec(n, Output(UInt(width=32))) + }) val pluses = Vec.fill(n){ Module(new IOCPlusOne).io } for (i <- 0 until n) { pluses(i).in := io.ins(i) @@ -28,7 +27,7 @@ class IOCModuleVec(val n: Int) extends Module { } class IOCModuleWire extends Module { - val io = new IOCSimpleIO + val io = IO(new IOCSimpleIO) val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType) inc.in := io.in io.out := inc.out -- cgit v1.2.3