From 2dce378deda1cc33833eb378c89a1c5415817bae Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 14:49:35 -0700
Subject: Distinguish between ?Int.Lit and ?Int.width

---
 src/test/scala/chiselTests/EnableShiftRegister.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')

diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 26af944f..5f3e0dd1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,9 +6,9 @@ import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt(4))
+    val in    = Input(UInt.width(4))
     val shift = Input(Bool())
-    val out   = Output(UInt(4))
+    val out   = Output(UInt.width(4))
   })
   val r0 = Reg(init = UInt(0, 4))
   val r1 = Reg(init = UInt(0, 4))
-- 
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