From 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Jan 2021 13:46:48 -0800
Subject: Rename MultiIOModule to Module

---
 src/test/scala/chiselTests/DataPrint.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/chiselTests/DataPrint.scala')

diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala
index beb92f0d..b5f96c4d 100644
--- a/src/test/scala/chiselTests/DataPrint.scala
+++ b/src/test/scala/chiselTests/DataPrint.scala
@@ -34,7 +34,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     } }
   }
 
-  class BoundDataModule extends MultiIOModule {  // not in the test to avoid anon naming suffixes
+  class BoundDataModule extends Module {  // not in the test to avoid anon naming suffixes
     Wire(UInt()).toString should be("UInt(Wire in BoundDataModule)")
     Reg(SInt()).toString should be("SInt(Reg in BoundDataModule)")
     val io = IO(Output(Bool()))  // needs a name so elaboration doesn't fail
@@ -44,7 +44,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers {
     (2.U + 2.U).toString should be("UInt<2>(OpResult in BoundDataModule)")
     Wire(Vec(3, UInt(2.W))).toString should be ("UInt<2>[3](Wire in BoundDataModule)")
 
-    class InnerModule extends MultiIOModule {
+    class InnerModule extends Module {
       val io = IO(Output(new Bundle {
         val a = UInt(4.W)
       }))
-- 
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