From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 32 +++++++++++-----------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index de75d07b..508c0849 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,17 +5,17 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
-import chisel3.internal.ExplicitCompileOptions
+import chisel3.ExplicitImplicitCompileOptions
 import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
-  abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
-  abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
+  abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict)
+  abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict)
 
   // Generate a set of options that do not have requireIOWrap enabled, in order to
   // ensure its definition comes from the implicit options passed to the Module constructor.
-  object StrictWithoutIOWrap extends ExplicitCompileOptions {
+  object StrictWithoutIOWrap extends ExplicitImplicitCompileOptions {
     val connectFieldsMustMatch = true
     val declaredTypeMustBeUnbound = true
     val requireIOWrap = false
@@ -35,7 +35,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class ConnectFieldMismatchModule extends Module {
         val io = IO(new Bundle {
@@ -49,7 +49,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class ConnectFieldMismatchModule extends Module {
       val io = IO(new Bundle {
@@ -63,7 +63,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class CreateRegFromBoundTypeModule extends Module {
         val io = IO(new Bundle {
@@ -77,7 +77,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class CreateRegFromBoundTypeModule extends Module {
       val io = IO(new Bundle {
@@ -90,7 +90,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
-    import chisel3.Strict.CompileOptions
+    import chisel3.ExplicitCompileOptions.Strict
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
@@ -103,7 +103,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 }
 
   "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
@@ -117,7 +117,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
@@ -134,7 +134,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -151,7 +151,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -170,7 +170,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     a [ChiselException] should be thrownBy {
       // Verify we can suppress the inclusion of default compileOptions
       import Chisel.{defaultCompileOptions => _, _}
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -191,7 +191,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -258,7 +258,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     object StrictNotIOWrap {
 
-      implicit object CompileOptions extends ExplicitCompileOptions {
+      implicit object CompileOptions extends ExplicitImplicitCompileOptions {
         val connectFieldsMustMatch = true
         val declaredTypeMustBeUnbound = true
         val requireIOWrap = false
-- 
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