From 1973e4d7333e2c57be4bcb7204210ecafdacab93 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 17:04:51 -0700
Subject: Check module-specific compile options. Import
 chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 180 +++++++++++++++++++++
 1 file changed, 180 insertions(+)
 create mode 100644 src/test/scala/chiselTests/CompileOptionsTest.scala

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
new file mode 100644
index 00000000..5bd3f959
--- /dev/null
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -0,0 +1,180 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import chisel3._
+import chisel3.core.Binding.BindingException
+import chisel3.testers.BasicTester
+
+class CompileOptionsSpec extends ChiselFlatSpec {
+
+  class SmallBundle extends Bundle {
+    val f1 = UInt(width = 4)
+    val f2 = UInt(width = 5)
+    override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type]
+  }
+  class BigBundle extends SmallBundle {
+    val f3 = UInt(width = 6)
+    override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
+  }
+
+  "A Module with missing bundle fields when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class ConnectFieldMismatchModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(new SmallBundle)
+          val out = Output(new BigBundle)
+        })
+        io.out := io.in
+      }
+      elaborate { new ConnectFieldMismatchModule() }
+    }
+  }
+
+  "A Module with missing bundle fields when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class ConnectFieldMismatchModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(new SmallBundle)
+        val out = Output(new BigBundle)
+      })
+      io.out := io.in
+    }
+    elaborate { new ConnectFieldMismatchModule() }
+  }
+
+  "A Module in which a Reg is created with a bound type when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class CreateRegFromBoundTypeModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(new SmallBundle)
+          val out = Output(new BigBundle)
+        })
+        val badReg = Reg(UInt(7, width=4))
+      }
+      elaborate { new CreateRegFromBoundTypeModule() }
+    }
+  }
+
+  "A Module in which a Reg is created with a bound type when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class CreateRegFromBoundTypeModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(new SmallBundle)
+        val out = Output(new BigBundle)
+      })
+      val badReg = Reg(UInt(7, width=4))
+    }
+    elaborate { new CreateRegFromBoundTypeModule() }
+  }
+
+
+  "A Module with wrapped IO when compiled with Strict.CompileOption " should "not throw an exception" in {
+    import chisel3.Strict.CompileOptions
+
+    class RequireIOWrapModule extends Module {
+      val io = IO(new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      })
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+}
+
+  "A Module with unwrapped IO when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class RequireIOWrapModule extends Module {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+      elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class SimpleModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(width = 3))
+          val out = Output(UInt(width = 4))
+        })
+      }
+      class SwappedConnectionModule extends SimpleModule {
+        val child = Module(new SimpleModule)
+        io.in := child.io.out
+      }
+      elaborate { new SwappedConnectionModule() }
+    }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class SimpleModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(width = 3))
+        val out = Output(UInt(width = 4))
+      })
+    }
+    class SwappedConnectionModule extends SimpleModule {
+      val child = Module(new SimpleModule)
+      io.in := child.io.out
+    }
+    elaborate { new SwappedConnectionModule() }
+  }
+
+  "A Module with directionless connections when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class SimpleModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(width = 3))
+          val out = Output(UInt(width = 4))
+        })
+        val noDir = Wire(UInt(width = 3))
+      }
+
+      class DirectionLessConnectionModule extends SimpleModule {
+        val a = UInt(0, width = 3)
+        val b = Wire(UInt(width = 3))
+        val child = Module(new SimpleModule)
+        b := child.noDir
+      }
+      elaborate { new DirectionLessConnectionModule() }
+    }
+  }
+
+  "A Module with directionless connections when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class SimpleModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(width = 3))
+        val out = Output(UInt(width = 4))
+      })
+      val noDir = Wire(UInt(width = 3))
+    }
+
+    class DirectionLessConnectionModule extends SimpleModule {
+      val a = UInt(0, width = 3)
+      val b = Wire(UInt(width = 3))
+      val child = Module(new SimpleModule)
+      b := child.noDir
+    }
+    elaborate { new DirectionLessConnectionModule() }
+  }
+}
-- 
cgit v1.2.3


From 5df671531c4a83dc17ecfdce6aecc8789d50fa7f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 30 Aug 2016 09:18:35 -0700
Subject: Add abstract classes with explicit connection checking options.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 81 +++++++++++++++++++---
 1 file changed, 70 insertions(+), 11 deletions(-)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 5bd3f959..5b27bf90 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -9,6 +9,9 @@ import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
+  abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
+  abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
+
   class SmallBundle extends Bundle {
     val f1 = UInt(width = 4)
     val f2 = UInt(width = 5)
@@ -19,7 +22,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
   }
 
-  "A Module with missing bundle fields when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -34,7 +37,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module with missing bundle fields when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class ConnectFieldMismatchModule extends Module {
@@ -47,7 +50,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new ConnectFieldMismatchModule() }
   }
 
-  "A Module in which a Reg is created with a bound type when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -62,7 +65,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module in which a Reg is created with a bound type when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class CreateRegFromBoundTypeModule extends Module {
@@ -75,8 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new CreateRegFromBoundTypeModule() }
   }
 
-
-  "A Module with wrapped IO when compiled with Strict.CompileOption " should "not throw an exception" in {
+  "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
     import chisel3.Strict.CompileOptions
 
     class RequireIOWrapModule extends Module {
@@ -89,7 +91,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new RequireIOWrapModule() }
 }
 
-  "A Module with unwrapped IO when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class RequireIOWrapModule extends Module {
@@ -102,7 +104,24 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       elaborate { new RequireIOWrapModule() }
   }
 
-  "A Module connecting output as source to input as sink when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class RequireIOWrapModule extends Module {
+        val io = new Bundle {
+          val in = UInt(width = 32).asInput
+          val out = Bool().asOutput
+        }
+        io.out := io.in(1)
+      }
+      elaborate {
+        new RequireIOWrapModule()
+      }
+    }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -120,7 +139,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module connecting output as source to input as sink when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class SimpleModule extends Module {
@@ -136,7 +155,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     elaborate { new SwappedConnectionModule() }
   }
 
-  "A Module with directionless connections when compiled with Strict.CompileOption " should "throw an exception" in {
+  "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
       import chisel3.Strict.CompileOptions
 
@@ -158,7 +177,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
   }
 
-  "A Module with directionless connections when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+  "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
     import chisel3.NotStrict.CompileOptions
 
     class SimpleModule extends Module {
@@ -177,4 +196,44 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
     elaborate { new DirectionLessConnectionModule() }
   }
+
+  "A Module with wrapped IO when compiled with explicit Strict.CompileOption " should "not throw an exception" in {
+
+    class RequireIOWrapModule extends StrictModule {
+      val io = IO(new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      })
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module with unwrapped IO when compiled with explicit NotStrict.CompileOption " should "not throw an exception" in {
+
+    class RequireIOWrapModule extends NotStrictModule {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module with unwrapped IO when compiled with explicit Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+
+      class RequireIOWrapModule extends StrictModule {
+        val io = new Bundle {
+          val in = UInt(width = 32).asInput
+          val out = Bool().asOutput
+        }
+        io.out := io.in(1)
+      }
+      elaborate {
+        new RequireIOWrapModule()
+      }
+    }
+  }
 }
-- 
cgit v1.2.3


From 1379a192ca1f6c05aeba454b81e19fb8356e6cf3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 30 Aug 2016 10:17:18 -0700
Subject: Add example of specific CompileOptions settings to tests.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 5b27bf90..70843c3e 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,6 +5,7 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
+import chisel3.internal.ExplicitCompileOptions
 import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
@@ -236,4 +237,29 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       }
     }
   }
+
+  "A Module with unwrapped IO when compiled with an explicit requireIOWrap false " should "not throw an exception" in {
+
+    object StrictNotIOWrap {
+
+      implicit object CompileOptions extends ExplicitCompileOptions {
+        val connectFieldsMustMatch = true
+        val declaredTypeMustBeUnbound = true
+        val requireIOWrap = false
+        val dontTryConnectionsSwapped = true
+        val dontAssumeDirectionality = true
+      }
+
+    }
+    class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+    elaborate {
+      new NotIOWrapModule()
+    }
+  }
 }
-- 
cgit v1.2.3


From 4b88a5dd45337fa88178fe17324eef3661daf1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 1 Sep 2016 10:21:57 -0700
Subject: Move connection implicits from Module constructor to connection
 methods. Eliminate builder compileOptions.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 25 ++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 70843c3e..f835ab0d 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -13,6 +13,16 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
   abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
 
+  // Generate a set of options that do not have requireIOWrap enabled, in order to
+  // ensure its definition comes from the implicit options passed to the Module constructor.
+  object StrictWithoutIOWrap extends ExplicitCompileOptions {
+    val connectFieldsMustMatch = true
+    val declaredTypeMustBeUnbound = true
+    val requireIOWrap = false
+    val dontTryConnectionsSwapped = true
+    val dontAssumeDirectionality = true
+  }
+
   class SmallBundle extends Bundle {
     val f1 = UInt(width = 4)
     val f2 = UInt(width = 5)
@@ -199,7 +209,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with explicit Strict.CompileOption " should "not throw an exception" in {
-
+    implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends StrictModule {
       val io = IO(new Bundle {
         val in = UInt(width = 32).asInput
@@ -207,11 +217,13 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       })
       io.out := io.in(1)
     }
-    elaborate { new RequireIOWrapModule() }
+    elaborate {
+      new RequireIOWrapModule()
+    }
   }
 
   "A Module with unwrapped IO when compiled with explicit NotStrict.CompileOption " should "not throw an exception" in {
-
+    implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends NotStrictModule {
       val io = new Bundle {
         val in = UInt(width = 32).asInput
@@ -219,12 +231,14 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       }
       io.out := io.in(1)
     }
-    elaborate { new RequireIOWrapModule() }
+    elaborate {
+      new RequireIOWrapModule()
+    }
   }
 
   "A Module with unwrapped IO when compiled with explicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-
+      implicit val strictWithoutIOWrap = StrictWithoutIOWrap
       class RequireIOWrapModule extends StrictModule {
         val io = new Bundle {
           val in = UInt(width = 32).asInput
@@ -256,7 +270,6 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val in = UInt(width = 32).asInput
         val out = Bool().asOutput
       }
-      io.out := io.in(1)
     }
     elaborate {
       new NotIOWrapModule()
-- 
cgit v1.2.3


From 8e2615fd3852c7ffa5ee1884cca0f77062f3cc21 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 6 Sep 2016 08:46:16 -0700
Subject: Verify we can suppress the inclusion of default compileOptions.

---
 src/test/scala/chiselTests/CompileOptionsTest.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index f835ab0d..de75d07b 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -168,6 +168,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with directionless connections when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
+      // Verify we can suppress the inclusion of default compileOptions
+      import Chisel.{defaultCompileOptions => _, _}
       import chisel3.Strict.CompileOptions
 
       class SimpleModule extends Module {
-- 
cgit v1.2.3


From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 32 +++++++++++-----------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index de75d07b..508c0849 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,17 +5,17 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
-import chisel3.internal.ExplicitCompileOptions
+import chisel3.ExplicitImplicitCompileOptions
 import chisel3.testers.BasicTester
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
-  abstract class StrictModule extends Module()(chisel3.Strict.CompileOptions)
-  abstract class NotStrictModule extends Module()(chisel3.NotStrict.CompileOptions)
+  abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict)
+  abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict)
 
   // Generate a set of options that do not have requireIOWrap enabled, in order to
   // ensure its definition comes from the implicit options passed to the Module constructor.
-  object StrictWithoutIOWrap extends ExplicitCompileOptions {
+  object StrictWithoutIOWrap extends ExplicitImplicitCompileOptions {
     val connectFieldsMustMatch = true
     val declaredTypeMustBeUnbound = true
     val requireIOWrap = false
@@ -35,7 +35,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class ConnectFieldMismatchModule extends Module {
         val io = IO(new Bundle {
@@ -49,7 +49,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class ConnectFieldMismatchModule extends Module {
       val io = IO(new Bundle {
@@ -63,7 +63,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class CreateRegFromBoundTypeModule extends Module {
         val io = IO(new Bundle {
@@ -77,7 +77,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class CreateRegFromBoundTypeModule extends Module {
       val io = IO(new Bundle {
@@ -90,7 +90,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
-    import chisel3.Strict.CompileOptions
+    import chisel3.ExplicitCompileOptions.Strict
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
@@ -103,7 +103,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 }
 
   "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
@@ -117,7 +117,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
@@ -134,7 +134,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -151,7 +151,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -170,7 +170,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     a [ChiselException] should be thrownBy {
       // Verify we can suppress the inclusion of default compileOptions
       import Chisel.{defaultCompileOptions => _, _}
-      import chisel3.Strict.CompileOptions
+      import chisel3.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -191,7 +191,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.NotStrict.CompileOptions
+    import chisel3.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -258,7 +258,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     object StrictNotIOWrap {
 
-      implicit object CompileOptions extends ExplicitCompileOptions {
+      implicit object CompileOptions extends ExplicitImplicitCompileOptions {
         val connectFieldsMustMatch = true
         val declaredTypeMustBeUnbound = true
         val requireIOWrap = false
-- 
cgit v1.2.3


From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 14:57:42 -0700
Subject: Consolidate CompileOptions and re-enable NotStrict pending macro
 work.

---
 .../scala/chiselTests/CompileOptionsTest.scala     | 33 +++++++++++-----------
 1 file changed, 17 insertions(+), 16 deletions(-)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 508c0849..83077544 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -5,17 +5,18 @@ package chiselTests
 import org.scalatest._
 import chisel3._
 import chisel3.core.Binding.BindingException
-import chisel3.ExplicitImplicitCompileOptions
+import chisel3.core.ExplicitCompileOptions
 import chisel3.testers.BasicTester
+import chisel3.core.CompileOptions
 
 class CompileOptionsSpec extends ChiselFlatSpec {
 
-  abstract class StrictModule extends Module()(chisel3.ExplicitCompileOptions.Strict)
-  abstract class NotStrictModule extends Module()(chisel3.ExplicitCompileOptions.NotStrict)
+  abstract class StrictModule extends Module()(chisel3.core.ExplicitCompileOptions.Strict)
+  abstract class NotStrictModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict)
 
   // Generate a set of options that do not have requireIOWrap enabled, in order to
   // ensure its definition comes from the implicit options passed to the Module constructor.
-  object StrictWithoutIOWrap extends ExplicitImplicitCompileOptions {
+  object StrictWithoutIOWrap extends CompileOptions {
     val connectFieldsMustMatch = true
     val declaredTypeMustBeUnbound = true
     val requireIOWrap = false
@@ -35,7 +36,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class ConnectFieldMismatchModule extends Module {
         val io = IO(new Bundle {
@@ -49,7 +50,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with missing bundle fields when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class ConnectFieldMismatchModule extends Module {
       val io = IO(new Bundle {
@@ -63,7 +64,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module in which a Reg is created with a bound type when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class CreateRegFromBoundTypeModule extends Module {
         val io = IO(new Bundle {
@@ -77,7 +78,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module in which a Reg is created with a bound type when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class CreateRegFromBoundTypeModule extends Module {
       val io = IO(new Bundle {
@@ -90,7 +91,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with wrapped IO when compiled with implicit Strict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.Strict
+    import chisel3.core.ExplicitCompileOptions.Strict
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
@@ -103,7 +104,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 }
 
   "A Module with unwrapped IO when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
@@ -117,7 +118,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module with unwrapped IO when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [BindingException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
@@ -134,7 +135,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
   "A Module connecting output as source to input as sink when compiled with implicit Strict.CompileOption " should "throw an exception" in {
     a [ChiselException] should be thrownBy {
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -151,7 +152,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module connecting output as source to input as sink when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -170,7 +171,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     a [ChiselException] should be thrownBy {
       // Verify we can suppress the inclusion of default compileOptions
       import Chisel.{defaultCompileOptions => _, _}
-      import chisel3.ExplicitCompileOptions.Strict
+      import chisel3.core.ExplicitCompileOptions.Strict
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
@@ -191,7 +192,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
+    import chisel3.core.ExplicitCompileOptions.NotStrict
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
@@ -258,7 +259,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     object StrictNotIOWrap {
 
-      implicit object CompileOptions extends ExplicitImplicitCompileOptions {
+      implicit object CompileOptions extends CompileOptions {
         val connectFieldsMustMatch = true
         val declaredTypeMustBeUnbound = true
         val requireIOWrap = false
-- 
cgit v1.2.3