From 5ecde24d390248722f8ab6ac790fbd1d453e898e Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Fri, 31 Jul 2020 11:05:13 -0700
Subject: Check whether signals escape their when scopes (#1518)

* Include and check when scoping as part of reg/mem/wire/node bindings

* Allow outdated 'when' behavior of CHIRRTL memory ports with enables

* Extend cross-module / when-visibility checks to all data refs

* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args

* Add basic test cases for cross-module refs / signals escaping when scopes

* Remove illegal cross-module references from existing tests---
 src/test/scala/chiselTests/CompileOptionsTest.scala | 19 -------------------
 1 file changed, 19 deletions(-)

(limited to 'src/test/scala/chiselTests/CompileOptionsTest.scala')

diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 092e6f11..120a6bf3 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -165,23 +165,4 @@ class CompileOptionsSpec extends ChiselFlatSpec with Utils {
     }
   }
 
-  "A Module with directionless connections when compiled with implicit NotStrict.CompileOption " should "not throw an exception" in {
-    import chisel3.ExplicitCompileOptions.NotStrict
-
-    class SimpleModule extends Module {
-      val io = IO(new Bundle {
-        val in = Input(UInt(3.W))
-        val out = Output(UInt(4.W))
-      })
-      val noDir = Wire(UInt(3.W))
-    }
-
-    class DirectionLessConnectionModule extends SimpleModule {
-      val a = 0.U(3.W)
-      val b = Wire(UInt(3.W))
-      val child = Module(new SimpleModule)
-      b := child.noDir
-    }
-    ChiselStage.elaborate { new DirectionLessConnectionModule() }
-  }
 }
-- 
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