From f45216effc573d33d4aa4e525cff955ab332efbd Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Thu, 4 Feb 2021 00:36:12 +0000
Subject: Remove Deprecated APIs (#1730)

---
 src/test/scala/chiselTests/CompatibilitySpec.scala | 56 ----------------------
 1 file changed, 56 deletions(-)

(limited to 'src/test/scala/chiselTests/CompatibilitySpec.scala')

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 6a77c821..c7a68e7c 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -103,7 +103,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       Reverse(wire) shouldBe a [UInt]
       Cat(wire, wire) shouldBe a [UInt]
       Log2(wire) shouldBe a [UInt]
-      unless(Bool(false)) {}
       // 'switch' and 'is' are tested below in Risc
       Counter(2) shouldBe a [Counter]
       DecoupledIO(wire) shouldBe a [DecoupledIO[UInt]]
@@ -353,13 +352,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
       info("Deprecated method DC hasn't been removed")
       val bp = BitPat.DC(4)
-
-      info("BitPat != UInt is a Bool")
-      (bp != UInt(4)) shouldBe a [Bool]
-
-      /* This test does not work, but I'm not sure it's supposed to? It does *not* work on chisel3. */
-      // info("UInt != BitPat is a Bool")
-      // (UInt(4) != bp) shouldBe a [Bool]
     }
 
     ChiselStage.elaborate(new Foo)
@@ -474,22 +466,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
   behavior of "Data methods"
 
-  it should "support legacy methods" in {
-    class Foo extends Module {
-      val io = IO(new Bundle{})
-
-      info("litArg works")
-      UInt(width=3).litArg() should be (None)
-      UInt(0, width=3).litArg() should be (Some(chisel3.internal.firrtl.ULit(0, 3.W)))
-
-      info("toBits works")
-      val wire = Wire(UInt(width=4))
-      Vec.fill(4)(wire).toBits.getWidth should be (wire.getWidth * 4)
-    }
-
-    ChiselStage.elaborate(new Foo)
-  }
-
   behavior of "Wire"
 
   it should "support legacy methods" in {
@@ -542,9 +518,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
       val u = UInt(8)
       val s = SInt(-4)
 
-      info("toBools works")
-      u.toBools shouldBe a [Seq[Bool]]
-
       info("asBits works")
       s.asBits shouldBe a [Bits]
 
@@ -553,35 +526,6 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
 
       info("toUInt works")
       s.toUInt shouldBe a [UInt]
-
-      info("toBool works")
-      UInt(1).toBool shouldBe a [Bool]
-    }
-
-    ChiselStage.elaborate(new Foo)
-  }
-
-  behavior of "UInt"
-
-  it should "support legacy methods" in {
-    class Foo extends Module {
-      val io = new Bundle{}
-
-      info("!= works")
-      (UInt(1) != UInt(1)) shouldBe a [Bool]
-    }
-
-    ChiselStage.elaborate(new Foo)
-  }
-
-  behavior of "SInt"
-
-  it should "support legacy methods" in {
-    class Foo extends Module {
-      val io = new Bundle{}
-
-      info("!= works")
-      (SInt(-1) != SInt(-1)) shouldBe a [Bool]
     }
 
     ChiselStage.elaborate(new Foo)
-- 
cgit v1.2.3


From 0a0d7c6aac4326f2127d6d95efa5a4e10c81946c Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 12 Oct 2020 21:02:27 -0700
Subject: Make it possible to GC Data instances

No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.

* Add MemTypeBinding for port types of Mems

This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.

* Call _onModuleClose on unbound Records

This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
---
 src/test/scala/chiselTests/CompatibilitySpec.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/test/scala/chiselTests/CompatibilitySpec.scala')

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index c7a68e7c..2d4ad517 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -451,6 +451,18 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     ChiselStage.elaborate(new Foo)
   }
 
+  it should "support data-types of mixed directionality" in {
+    class Foo extends Module {
+      val io = IO(new Bundle {})
+      val tpe = new Bundle { val foo = UInt(OUTPUT, width = 4); val bar = UInt(width = 4) }
+      // NOTE for some reason, the old bug this hit did not occur when `tpe` is inlined
+      val mem = SeqMem(tpe, 8)
+      mem(3.U)
+
+    }
+    ChiselStage.elaborate((new Foo))
+  }
+
   behavior of "debug"
 
   it should "still exist" in {
-- 
cgit v1.2.3